KR980012151A - Scribe Line Scribe Line Semiconductor chip of TAB product with reduced width - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip in which a scribe line width of a semiconductor chip is reduced in order to prevent defects due to sagging of a tab lead during a manufacturing process of a TAB product, Even when the tap lead is sagged between the semiconductor chip and the tap film during the internal lead bonding (ILB) of the tap product to cause a deflection phenomenon of the tab lead to come into contact with the edge portion of the semiconductor chip, Since the contact between the tab lead and the chip edge does not occur, the defective characteristics of the chip can be prevented, the total number of the individual semiconductor chips formed on the wafer is increased, and the productivity is improved. The number of steps increases, and the process of moving the pattern of the mask onto the wafer is shortened.

Description

Scribe Line Scribe Line Semiconductor chip of TAB product with reduced width

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor chip of a TAB product having a reduced scribe line width, and more particularly, To a semiconductor chip with reduced scribe line width.

BACKGROUND ART Tape Automated Bonding (TAB) is one of electrical connection methods between a semiconductor chip and a printed circuit board, and is comparable to conventional wire bonding. That is, the wire bonding is a method in which the pads of the chip and the leads of the lead frame are individually connected as metal wires via a lead frame, whereas the TAB is a method in which leads are patterned in advance It has the advantage that the chip pads and the TAB leads can be bonded together (gang bonding) by using a film.

Such a TAB method is used in various semiconductor products including a thin film transistor (TFT) liquid crystal display (LCD) driver.

FIG. 1 is a perspective view showing a state in which a general tab lead and a semiconductor chip are internal lead-bonded, and FIG. 2 is a cross-sectional view showing a section cut along the line 2-2 in FIG.

1 and 2, a TAB product 10 includes tab tapes 12 on which a plurality of tab leads 14 are patterned. On the tab tapes 12, An opening 17 is formed for electrical connection between the tab leads 14 and the semiconductor chip 20. Four or two windows 16 are formed around the opening 17 and the top leads 14 extend to the inside of the opening 17 across the window 16.

The window 16 may have a shape such that the tab film 12 penetrates the opening 17 like the opening 17 and the tab leads 14 may be formed on the external substrate It is a window opening to be electrically bonded and connected. The tab leads 14 extending inwardly of the opening 17 are referred to as an inner lead and the tab leads 14 traversing the window 16 are called an outer lead.

A plurality of sprocket holes 18 are formed on both side surfaces of the tap film 12 so that the tap film 12 can be automatically supplied in a reel shape. The tap film 12 is typically of the plastic resin type such as polyimide, and the tab lead 14 is a kind of copper alloy such as a typical lead frame.

The tap film 12 having the tab lead 14 patterned as described above is electrically connected to the semiconductor chip 20 through the opening 17. [ A plurality of chip pads 26 are formed and arranged on the upper surface of the semiconductor chip 20 and bumps 28 are formed on the chip pads 26. The semiconductor chip 20 is positioned under the tab leads 14, that is, the internal leads extending and formed inside the opening portion 17, the internal leads and the bumps 28 are aligned, Bonded at the same time. This is called Inner Lead Bonding (ILB).

Then, in a similar manner, the outer lead portion of the tab lead 14 is physically and electrically connected and connected to an external substrate (not shown) through the window 16. [ This is called outer lead bonding (OLB). Fig. 1 shows a shape before internal lead bonding is completed and external lead bonding is performed.

Fig. 3 is a cross-sectional view showing an enlargement of the portion "A" in Fig. 2 and showing defects due to the deflection phenomenon of the tab lead according to the prior art.

1 to 3, the tab product 10 is sandwiched between each semiconductor chip 20 and the tap film 12 in the tab lead 14 during internal lead bonding, and contacts the edge portion of the semiconductor chip 20 . That is, the tap lead portion between the opening portion 17 and the window 16, that is, the tab lead portion formed on the tap film 12 and the tab lead portion between the opening 17 and the window 16 are connected to the bump 28 A difference in height of the tab lead portion is generated. This phenomenon is called a lead sagging phenomenon.

If the lead deflection phenomenon occurs, characteristic failure may easily occur when the semiconductor chip 20 is operated. The semiconductor chip 20 is divided into a main chip 22 and a scribe line 24 'so that the chip scribe line 24' And extends to the bottom surface of the main chip 22, which is a ground region. Therefore, when the tab lead 14 and the chip scribe line 24 'come into contact with each other due to the lead deflection phenomenon, a voltage value of 0 V or more is obtained from the bump 28 formed on the chip pad 26 when the semiconductor chip 10 operates The output of the chip scribe line 24 'is formed to the ground region through the chip scribe line 24', thereby causing a characteristic failure, which is not a normal operation.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor chip in which the scribe line width can be reduced to prevent defective characteristics of the chip by preventing contact between the tab lead and the chip edge even when the tab lead is deflected.

FIG. 1 is a perspective view showing a state where a general tab lead and a semiconductor chip are internally lead-bonded. FIG.

FIG. 2 is a cross-sectional view taken along line 2-2 of FIG. 2;

3 is a cross-sectional view showing an enlargement of the portion "A" in FIG. 2, showing defects due to the deflection phenomenon of the tab lead according to the prior art.

FIG. 4 is a cross-sectional view showing a part of a semiconductor chip with reduced scribe line width according to an embodiment of the present invention; FIG.

5 is a plan view showing a mask for manufacturing semiconductor chips according to an embodiment of the present invention shown in FIG. 4; FIG.

FIG. 6 is a plan view of the "B" portion of FIG. 5 enlarged and showing the cut regions in the wafer state together.

FIGS. 7A and 7B are partial plan views comparing sizes of an example of a semiconductor chip according to the conventional technology and the present invention. FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

10: TAB Product 12: TAB Film

14: TAB Lead 16: Window (Lead)

17: opening (opening) 18: sprocket hole

20: semiconductor chip (Chip) 22: main chip (Main Chip)

24, 24 ': Chip Scribe Line 26: Chip Pad

28: Bump 30: Mask

32: main chip pattern (main chip pattern) 34: mask scribe line

40: Sawing area

In order to accomplish the above object, the present invention provides a semiconductor integrated circuit device, comprising: a main chip having semiconductor integrated circuit elements, a metal wiring electrically connecting the elements to each other, and a chip pad serving as an electrical connection path between the elements and the external substrate; And a chip scribe line surrounding the outer periphery of the main chip with a predetermined width and extending to a bottom surface of the main chip, wherein the chip scribe line has a width of 20 μm to 25 μm .

A plurality of main chip patterns having a pattern of semiconductor integrated circuit elements and a metal wiring pattern for electrically connecting the elements to each other; And a mask scribe line for separating each of the main chip patterns into a predetermined width. The mask scribe line has a width of 80 m.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings.

FIG. 4 is a cross-sectional view showing a part of a semiconductor chip with a reduced scribe line width according to an embodiment of the present invention, FIG. 5 is a plan view showing a mask for manufacturing semiconductor chips according to an embodiment of the present invention shown in FIG. FIG. 6 is a plan view showing a cut-away region in a wafer state by enlarging a portion "B" in FIG. 5, and FIGS. 7A and 7B illustrate an example of a semiconductor chip of the prior art and the present invention, Fig.

4 to 7 and FIGS. 1 and 2, the semiconductor chip 20 of the present invention is roughly divided into a main chip 22 and a chip scribe line 24, similar to the conventional semiconductor chip. The chip scribe line 24 includes an oxide film, a polycrystalline silicon layer, a metal wiring layer, an insulating film, and the like as a part where the semiconductor integrated circuit elements are formed. The outer periphery of the main chip 22 is surrounded by a predetermined width d and extends to the bottom surface of the main chip 22. The chip scribe line 24 is a region remaining after being separated by cutting means when the chips in the wafer state are sown or separated into individual chips.

In the embodiment of the present invention, the chip scribe line width d is reduced. The method is accomplished through modification of the mask 30 for manufacturing the semiconductor chip 20. As shown in FIG. 5, the semiconductor chip 20 of a thin film transistor liquid crystal display driver (TFT LCD Driver) is patterned with three to seven main chips 32 per one mask 30. A mask scribe line 34 separating the main chip patterns 32 into a predetermined width w is formed. Therefore, the semiconductor chip 20 of the present invention can be manufactured by reducing the width (w) of the mask scribe line in the state of the mask 30.

Conventionally, the mask scribe line width w, which is generally Tm, is 170 m. This is reduced to 80 탆 in the present invention. The width w is also a threshold value that can be reduced on the mask 30. [ However, the chip scribe line width d may vary depending on the width s of the cutting means. However, in consideration of the chip scribe line width (d) and the impact applied to the chip at the time of cutting, the cutting means having a width (s) of 30 탆 and 40 탆 is used at present.

(1) When the width (s) of the cutting means is 30 mu m and the mask scribe line width (w) is reduced from 170 mu m to 80 mu m, the chip scribe line width d is reduced from 70 mu m to 25 mu m. This can be confirmed by the following equations (1) and (6).

(2) When the width (s) of the cutting means is 40 占 퐉 and the mask scribe line width (w) is reduced from 170 占 퐉 to 80 占 퐉, the chip scribe line width d is reduced from 65 占 퐉 to 20 占 퐉.

The following is summarized.

Therefore, according to the structure of the present invention, since the chip scribe line, which is the outer portion of the semiconductor chip, is reduced to reduce the overall size of the chip, even if the tab lead deflects, contact between the tab lead and the chip edge does not occur, There is an advantage to be able to do.

However, even if the position of the chip pad is moved toward the chip periphery without decreasing the width of the chip scribe line as in the above-described embodiment, the same effect as that of the present embodiment will be obtained. That is, in the case of a conventional semiconductor chip in which the chip pad is formed at a position within 30 mu m from the edge of the main chip, if the distance is reduced to 10 mu m, the same effect as that in the present embodiment can be obtained by reducing the width of the chip scribe line by 20 mu m will be. However, even in this case, since the maximum deceleration limit width is only 30 占 퐉, the effect is less than that of the present embodiment.

According to the structure of the present invention, not only the advantage but also the total number of semiconductor chips formed on the wafer is increased.

For example, assuming that a 6 inch waferer commonly used in a thin film transistor liquid crystal display driver (TFT LCD Driver) is used as a reference, and the width s of the cutting means is 30 mu m,

(1) When the size ab of the main chip on the mask is 10005 탆 and 1005 탆 and the mask scribe line width w is reduced from 170 탆 to 80 탆, (a + 2d) (b + 2d)) is reduced from 10145 mu m to 1155 mu m to 10055 mu m and to 1055 mu m, and the total number of individual chips increases from 1272 to 1399.

(2) When the size (ab) of the main chip on the mask is 9905 탆 and 905 탆, and the mask scribe line width (w) is reduced from 170 탆 to 80 탆, (a + 2d) (b + 2d)) is reduced from 10045 占 퐉 1045 占 퐉 to 9955 占 퐉 955 占 퐉, and the total number of individual chips increases from 1415 to 1569.

The following is summarized.

Thus, not only the total number of semiconductor chips formed on the wafer increases but also the number of main main chip patterns patterned on the mask can be increased. That is, the number of main chip patterns per one mask can increase up to eight according to the mask's allowable range.

The advantages of the above-described structure of the present invention are as follows.

(1) Since the chip scribe line, which is the outer part of the semiconductor chip, is reduced and the overall size of the chip is reduced, contact between the tab lead and the chip edge does not occur even if the tab lead deflection phenomenon occurs.

(2) Since the total number of individual semiconductor chips formed on the wafer increases, productivity is improved.

(3) Since the total number of main chip patterns to be patterned on the mask is increased, the process of transferring the pattern of the mask onto the wafer is shortened.

Claims (6)

A main chip having semiconductor integrated circuit elements, a metal wiring electrically connecting the elements to each other, and a chip pad serving as an electrical connection path between the elements and the external substrate; And a chip scribe line surrounding the outer periphery of the main chip with a predetermined width and extending to a bottom surface of the main chip, wherein the chip scribe line has a width of 20 to 25 mu m. The semiconductor chip according to claim 1, wherein a bump is formed on a chip pad of the main chip. The semiconductor chip according to claim 2, wherein the bumps and the external substrate are electrically connected by a tapping method. The semiconductor chip according to claim 1, wherein the semiconductor chip is used in a transistor liquid crystal display driver. A plurality of main chip patterns having a pattern of semiconductor integrated circuit elements and a metal wiring pattern for electrically connecting the elements to each other; And a mask scribe line for separating each of the main chip patterns into a predetermined width, wherein the width of the mask scribe line is 80 占 퐉. The mask for manufacturing a semiconductor chip according to claim 5, wherein the mask is a mask used for manufacturing a semiconductor chip used in a thin film transistor liquid crystal display driver. ※ Note: It is disclosed by the contents of the first application.