KR980011417A - A latch-type sense amplifier unit having negative feedback means - Google Patents

Abstract

The present invention is equipped with negative feedback means for connecting the output portion of the sense amplifier circuit and the bit line after being enabled to prevent the potential difference of the bit line pair from being widened more than necessary when the conventional latch type sense amplifier section is applied A first switching means for on / off operation by an enable signal and for initiating a system operation during a turn-on operation; Second switching means for performing an initial operation of the system by performing on / off operations according to voltage states of data held in two data lines in a state that the first switching means is turned on; Third switching means which is turned on by the precharge signal and initializes the potentials of the two output signals; Latch means for latching data input through the second switching means according to the operation of the third switching means and outputting the data to two data output terminals; And a data line connected to one of the data output terminal and the data line of the latch means and being turned on / off according to a voltage state of the other data output terminal, And a feedback switching means for pulling up the potential difference of the output terminal.

Description

A latch-type sense amplifier unit having negative feedback means

FIG. 1 is a circuit diagram of a conventional latch type sense amplifier.

FIG. 2 is a circuit diagram of a memory read using a sense amplifier shown in FIG.

FIG. 3 shows an example of the operation waveform of the main part in the circuit operation of FIG. 2; FIG.

FIG. 4 is a circuit configuration diagram of a latch type sense amplifier according to the present invention; FIG.

FIG. 5 is a circuit diagram of a memory read using the sense amplifier shown in FIG.

FIG. 6 shows an example of the operation waveform of the main part in the circuit operation of FIG. 5; FIG.

7 is another embodiment of a latch type sense amplifier according to the present invention.

The present invention relates to a sense amplifier used in a memory device. In particular, in order to prevent a potential difference of a bit line pair from becoming unnecessarily widened when a conventional latch type sense amplifier is applied, And a latch type sense amplifier unit having negative feedback means for connecting lines.

Generally, a sense amplifier refers to a circuit that detects a voltage or a current level of an input signal as a threshold value and then amplifies and outputs the threshold voltage, and further includes a function of detecting only an input signal in a specific time domain.

Such a sense amplifier is generally used for a small output signal of a memory device or the like.

As described above, a sense amplifier used in a memory device may be a latch type. Referring to FIG. 1, which is a device referred to as a current driven latch type sense amplifier, a latch type will be described with reference to FIG.

FIG. 1 is a circuit configuration diagram of a conventional latch type sense amplifier. Referring to FIG. 1, there is shown a circuit diagram of a conventional latch type sense amplifier. A fourth PMOS transistor (MP3, MP4), a first PMOS transistor (MP3, MP4), and a second PMOS transistor A first PMOS MP1 connected to a drain terminal of the fourth PMOS MP4 and a second PMOS MP4 receiving a positive voltage VCC at a source terminal thereof and a common drain terminal connected to the common drain terminal of the fourth PMOS MP4 and the first PMOS MP1, And a drain terminal connected to a drain terminal of the third PMOS MP3 and a second PMOS MP2 connected between the fourth PMOS MP4 and the first PMOS MP1 Drain terminal is connected to the drain of the second PMOS transistor MP2, A gate terminal is connected to the common drain terminal of the third PMOS MP3 and the second PMOS MP2 and a gate terminal is connected to the drain terminal of the fourth PMOS MP4 and the first PMOS MP1 A fifth NMOS MN5 having a gate terminal connected to a common drain terminal of the fourth MNOS MN4 and a first data line DATA connected to a drain terminal of the fourth MNOS MN4 and connected to a gate terminal And a second data line (DATAB) connected to a drain terminal of the fifth NMOS transistor MN5 and connected to a gate terminal of the fifth NMOS transistor MN5. The second NMOS transistor MN5 is turned on / And a source terminal connected to a source terminal of the second NMOS MN2 and a drain terminal connected to a common source terminal of the second and third NMOSs MN2 and MN3. Is turned on / off by an enable signal (SAC) And a first NMOS MN1 that operates.

The sense amplifier unit configured as above is an example of a latch type, and is called a current driven latch type sense amplifier unit. Operations of the respective components will be described below.

The first NMOS transistor MN1 is turned on / off by the enable signal SAC and is turned on to start the operation of the sense amplifier. The second NMOS transistor MN2 and the third NMOS transistor MN3 are means for inputting data read from a memory cell not shown through the data lines DATA and DATAB to perform the initial operation of the sense amplifier section. The fourth and fifth NMOS transistors MN4 and MN5 and the first and second PMOS transistors MP1 and MP2 are latch sections and the third and fourth PMOS transistors MP3 MP4 are turned on by the precharging signal SEAQ, , SOUTB).

Referring to FIG. 2, which shows a read circuit of a memory using a conventional sense amplifier unit that performs the above-described function, the data values are stored and the voltage values of the word lines WL are A memory cell 50 connected in parallel to the bit lines BIT and BITB connected to the memory cell 50 and connected to the bit lines BIT and BITB via the bit lines BIT and BITB, A bit line precharge section 40 for precharging and equalizing the bit lines BIT and BITB by a first column selection signal YSW and a second column selection signal YSW having a phase opposite to the first column selection signal YSW, A column selection unit 30 connected to the column selection unit 30 and controlled by a data line YSWB and connecting the bit lines BIT and BITB with data lines DATA and DATAB; DATAB) and are connected in parallel to the control signal (CDTQ) A data line precharge section 20 connected in parallel to the data lines DATA and DATAB for equalizing and equalizing the data lines DATA and DATAB by a control signal CDTQ, And a sense amplifier unit 10 for receiving the data input through the data lines DATAB and amplifying the received data.

Although only one memory cell 50 is shown in FIG. 2, a plurality of memory cells of the same configuration are provided in parallel on the bit lines BIT and BITB.

Since the structure of the memory read circuit as described above is conventional, the detailed structure of each component will be omitted, and the operation characteristics of the structure constituting the memory read circuit will be described below.

When the word line WL is selected to the specified row address combination and the bit line is selected by the column address combination, that is, when the first column select signal YSW is high and the second column select signal YSWB is low The data stored in the memory cell 50 enters the input terminal of the sense amplifier unit 10 through the bit lines BIT and BITB and the data lines DATA and DATAB.

The bit line precharge section 40, which is not referred to in the description of the operation, is for precharging the potential level of the bit line (BIT, BITB) before the selected word line is enabled. That is, the PMOSs MP21 and MP22 of the PMOS MP21 to MP25 constituting the bit line precharge section 40 perform a function of pulling up the bit lines BIT and BITB to a predetermined positive voltage (VCC) level , And the PMOS (MP25) performs an equalization function to equalize the potential difference between the bit lines (BIT and BITB). The PMOSs MP23 and MP24 keep the level of the bit lines BIT and BITB at the positive voltage VCC in the static state and the potential difference of the bit lines BIT and BITB during the read operation becomes excessive .

Similar to the bit line precharge section 40, the data line precharge section 20 has the same function as the bit line precharge section 40, and the PMOS MP11 to MP13 correspond to the circuit configurations of reference numerals MP25, MP21 and MP22 in the configuration of the bit line precharge section 40, respectively.

As described above, the operation of the memory read circuit has been roughly described. The role and the problem of the sense amplifier used in the conventional memory read circuit operating as described above will be described in detail with reference to the above- do.

The data lines DATA and DATAB are precharged to the level of the positive voltage VCC and the enable signals SAC and the precharged signals SEAQ) is in a low state (see also Figure 3 (c)). The third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned on so that the potentials of the two output nodes are set at the positive voltage VCC ) To the level of.

The control signals CDEQ and DTEQ, which are input to the precharge sections 20 and 30 which are responsible for the precharge of the data line and the bit line when the word line and the column are opened and the bit line and the data line are precharged, (See also FIG. 3 (b)), the potential of the portion of the two bit lines connected to the row node of the memory cell 50 is pulled down and the potential difference of the bit line pair starts to be generated .

After a certain time from this, the enable signal SAC and the precharge signal SEAQ are turned high to terminate the precharging of the sense amplifier 10 and start sensing the input potential difference See also c). The minimum potential difference DV1 (see also FIG. 3 (d)) of the pair of bit lines for preventing the sense amplification unit 10 from malfunctioning is determined by the offset voltage Vdffset generated by the asymmetric element of the sense amplifier unit 10, .

The second NMOS transistor MN2 and the third NMOS transistor MN3 used as input terminals of the sense amplifier section 10 convert the potential difference between the data lines DATA and DATAB into a current difference. At this time, the discharge speed of the output portion becomes different due to the converted current difference, so that a potential difference occurs on both the sides of the output portion. Also, the latch unit formed of the NMOSs MN4 and MN5 and the PMOSs MP1 and MP2 attenuates the potential difference of the output unit so that the output unit latches at a high speed.

When the potential of the first data line DATA is higher than the potential of the second data line DATTB, the first output signal SOUT is latched high and the second output signal SOUTB is latched low. Once the latch is established, the first output signal SOUT is kept high by the second PMOS MP2 and the fifth NMOS MN5 is turned off. On the other hand, the second output signal SOUTB is held in a low state by the first, second and fourth NMOSs MN4, MN2 and MN1, and the first PMOS MP1 is turned off.

After the sense amplifier unit 10 is latched, the latched state remains unchanged even when the potential difference of the data lines DATA and DATTB is changed or even inverted. Therefore, the use of such a latch type sense amplification unit has an advantage that safety in operation can be secured.

On the other hand, when there is an asymmetry in the sense amplifier section 10, a potential difference sufficient to offset the offset voltage due to the asymmetry is applied to the input terminal. This is because, after the word line is selected, It must be enabled.

In order to reduce the time delay, the equivalent resistance of the PMOS (MP23, MP124) functioning as a DC pullup must be increased in the configuration of the bit line precharge section (40).

However, as shown in the accompanying FIG. 3, even after the sense amplifier unit 10 is latched, the potential difference of the bit line pair continues to increase and saturates at a value of dV2 (see also FIG. 3 , This value is determined according to the ratio of the current driving force of the memory cell to the current driving force of the DC pull-up.

However, in order to quickly precharge the bit line when the address is changed and the read operation for data of another memory cell is started, the smaller the size of DV2, the better. For this, the equivalent resistance of the DC pullup must be small.

Therefore, in order to reduce the time delay related to the enable of the sense amplification part, the equivalent resistance of the DC pull-up must be large. In order to accelerate the pre-charge speed during the address conversion, There arises a problem that the design becomes a considerable difficulty.

An object of the present invention to overcome the above problems is to provide a nonvolatile semiconductor memory device in which a negative feedback means is provided to enable the latch type sense amplification unit to be enabled and then to connect the output portion of the sense amplifier circuit and the bit line by the negative feedback means, And a negative feedback means for preventing the potential difference of the pair from widening more than necessary.

Also, the present invention provides a memory read circuit capable of applying a latch type sense amplifier unit having negative feedback means provided according to the above-described object.

According to an aspect of the present invention, there is provided a sense amplifier unit used in a memory device, including: first switching means for on / off operation by an enable signal and for initiating a system operation during a turn- Second switching means for turning on and off the first and second data lines in response to a voltage state of data held in two data lines in a state that the first switching means is turned on, Latch means for latching the data input through the second switching means and outputting the data to two data output stages in accordance with the operation of the third switching means and latch means for latching the data of the latch means Output terminal and the data line and is turned on / off according to the voltage state of the other data output terminal And a feedback switching means for pulling up the potential difference of the bit line connected to the data line by the potential applied to the corresponding data output terminal.

According to another aspect of the present invention, there is provided a sense amplifier unit for use in a memory device, comprising: first switching means for performing an on / off operation by an enable signal and initiating a system operation during a turn- Second switching means for turning on and off according to a voltage state of data held in two data lines in a state in which the first switching means is turned on and performing an initial operation of the system, Latch means for latching data input through the second switching means in response to an operation of the third switching means and outputting the data to two data output terminals, and latch means for latching data of the latch means Output terminal and the data line, and is turned on / off according to an external control signal. It is used to include a feedback pull-up switching means for the potential difference of the bit line that is associated with the data line to the potential applied to the data output terminal.

According to another aspect of the present invention, there is provided a semiconductor memory device including: a plurality of memory cells storing contradictory data values and outputting data stored on a bit line according to a voltage state of a word line by a specified row address combination; A bit line precharge unit connected in parallel to a bit line connected to the memory cell for equalizing and equalizing the bit line by a control signal, A column selection unit connected to the column selection unit and connected to the bit line and the data line, the parallel selection being controlled by a two column selection signal, and a data line connected in parallel to the column selection unit, A data line precharge section for making an equalization, and data input through the data line, The sense amplifier amplifies the potential difference between the bit line connected to the data line and the data output terminal. The memory read circuit amplifies and outputs the amplified bit line. And a feedback switching means for pulling up the potential of the bit line connected to the data line at a potential which is applied to the corresponding data output terminal in an ON / OFF operation by the sensed arbitrary control signal, and the bit line pre- And a switching means for on / off operation in response to a first column selection signal input to the column selection unit and for pulling up a corresponding bit line with a predetermined positive voltage in an on operation, wherein the bit line precharge unit includes a word line After selection, the bit line pair's row node It has to be configured to have a larger equivalent resistance.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 4 is a circuit diagram of a latch type sense amplifier unit according to the present invention. FIG. 4 is a circuit diagram of a latch type sense amplifying unit according to the present invention, in which a predetermined positive voltage VCC is input to a source terminal and an on / off operation is performed by a precharge signal SEAQ applied to a gate terminal And a third PMOS transistor MP103 which receives the positive voltage VCC at a source terminal and receives a voltage applied to a drain terminal of the third PMOS transistor MP103 to a gate terminal, A first PMOS MP101 having a terminal connected to the drain terminal of the fourth PMOS MP104 and a second PMOS MP101 receiving the positive voltage VCC at a source terminal thereof and receiving a common drain terminal of the fourth PMOS MP104 and the first PMOS MP101, A second PMOS MP102 connected to the drain terminal of the third PMOS MP103 and a fourth PMOS MP104 connected to the drain of the first PMOS MP103, A drain terminal is connected to a common drain terminal of the transistor MP101, 3PMOS (MP103) and a is a gate terminal connected to the common drain terminal of the 2PMOS (MP102) 4NMOS

A drain terminal is connected to a common drain terminal of the third PMOS MP103 and a second PMOS MP102 and a gate terminal is connected to a common drain terminal of the fourth PMOS MP104 and the first PMOS MP101 A second NMOS (MN105) having a drain terminal connected to a source terminal of the fourth NMOS (MN104) and a second NMOS (MN104) connected to a gate terminal, the second NMOS The second NMOS transistor MN105 has a drain terminal connected to the source terminal of the fifth NMOS transistor MN105 and is turned on / off according to the data state of the data line DATAB connected to the gate terminal. A third NMOS transistor MN103 connected to the source terminal of the second NMOS transistor MN102 and a third transistor MN103 having a drain terminal connected to the common source terminal of the second and third NMOS transistors MN102 and MN103 and an enable signal SAC A first NMOS (MN101) which is turned on / off by a first output A source terminal is connected to a common drain terminal of the first PMOS transistor MP101 and a fourth PMOS transistor MP104 and a gate terminal of the fourth NMOS transistor MN104 is input to a gate terminal thereof, A fifth PMOS (MP105) for outputting a potential to be supplied to a source terminal through a drain terminal connected to a first data line (DATA) connected to a gate terminal of the second NMOS (MN102), and a fifth PMOS The third NMOS transistor MN103 is turned on / off by receiving a signal applied to the gate terminal of the fifth NMOS transistor MN105 through a source terminal connected to the common drain terminal of the third PMOS transistor MP102 and the third PMOS transistor MP103, And a sixth PMOS (MP106) for outputting a potential to be supplied to a source terminal through a drain terminal to which a second data line DATAB connected to a gate terminal of the sixth PMOS is connected.

The difference between the configuration of the sense amplifier unit according to the present invention shown in FIG. 4 and the configuration of the conventional sense amplifier unit shown in FIG. 1 is that the means for connecting the output terminal of the sense amplifier unit and the data line, , MP106) are added.

FIG. 5 shows a read circuit of a memory using a sense amplifier according to the present invention.

The difference in configuration between the memory read circuit according to the present invention shown in FIG. 5 and the conventional memory read circuit shown in FIG. 2 is that the bit line precharge section 40A is provided with a column select section 30A A PMOS (MP126, MP127) is turned on according to the first column select signal YSW of the first column select signal YSW to precharge the bit line with a predetermined positive voltage VCC.

The basic operations of the sense amplifiers and the memory read circuits shown in FIGS. 4 and 5 are the same as those of the circuits shown in FIGS. 1 and 2, so that a detailed description of the basic operation will be omitted, Only the operation of the circuit according to the present invention corresponding to the portion of FIG.

When the sense amplifier unit 10A is in the precharged state, the fifth PMOS MP105 and the sixth PMOS MP106 are turned off.

When the sense amplifier unit 10A is enabled and the output is latched, one of the fifth PMOS MP105 and the sixth PMOS MP106 is turned on.

At this time, when the first output signal SOUT is high and the second output signal SOUTB is low, for example, because the potential of the first data line DATA is higher than the potential of the second data line DATAB , The fifth PMOS (MP105) is turned off, and the sixth PMOS (MP106) is turned on.

As a result, the current flowing through the second PMOS MP102 and the sixth PMOS MP106 charges the second data line DATAB and the potential level of the second data line DATAB rises. Therefore, And the potential difference between the second data line DATAB and the potential difference of the bit line (see dV5 in FIG. 6 (d)) are also reduced.

Therefore, there is an advantage that the bit line free chasing time is advantageously obtained at the time of address conversion.

Also, in the memory read circuit proposed to utilize the negative feedback characteristic in the sense amplifier section 10A as described above, the DC pull-up function among the PMOS (MP121 to MP127) constituting the bit line precharge section 30A The performance of the PMOS (MP123, MP124) is made to have an increased equivalent resistance as compared to the conventional case, so that the row-row pair of the bit line pair can be quickly discharged after the word line is selected.

Therefore, the delay time until the input potential difference of the sensing circuit reaches the offset voltage (see dV3 in the sixth (D)) can be reduced. In some cases, it may be designed such that the DC pullup (MP123, MP124) is omitted in the bit line.

The potential of the bit line of the selected column is reduced by the feedback means of the sense amplifier as described above. On the other hand, when the word line is selected in the unselected column to make a potential difference between the bit line pairs, the equivalent resistance of the DC pull-up is very large, so that the potential difference should not be excessive.

In order to accomplish this object, bit line pull-up means (MP126, MP127) controlled by the first column select signal YSW are added.

When the column is selected, since the PMOSs (MP126 and MP127) are in the turned off state, the read operation is performed as described above. On the other hand, if the column is not selected, the PMOS transistors MP126 and MP127 are turned on. Since the current driving force of the pull-up means is much larger than the current driving force of the memory cell, the potential difference of the bit line pair has a small value.

Therefore, a latch type sense amplifier having negative feedback means according to the present invention and a memory read circuit according to the present invention provide a problem that has been presented as a conflicting difficulty in the design of a conventional memory access circuit, In order to reduce the time delay associated with the enable, the equivalent resistance of the DC pull-up must be large, and in order to speed up the precharging speed during the address conversion, there is an effect that the conflicting requirement that the equivalent resistance of the DC pull-

The feature of the sense amplifier section proposed in the detailed description of the present invention is to feed back the output signals (SOUT and SOUTB) of the amplification section to the data lines. The control signals are used as the output signals SOUT and SOUTB will be. Unlike this embodiment, there may be an embodiment in which the control signal is operated by a delay circuit (not shown).

7, the characteristics of the sense amplifier circuit shown in FIG. 7 are such that the output operation of the sense amplifier and the data line are cut off before the latch operation is completed, It can be done more quickly than the existing circuit.

On the other hand, the disadvantage of the sense amplifier circuit shown in Fig. 7 is that the potential difference between the bit lines increases immediately before the feedback (see also dV4 in Fig. 6 (d)). This is a factor that slows down the speed.

However, dV4, which is an increment of the potential difference between the bit lines immediately before the feedback, which is presented as a disadvantage of the sense amplifier circuit shown in FIG. 7, is smaller than the maximum of the bit line potential difference (see FIG. A clear effect can be obtained compared with the technique.

Claims (4)

1. A sense amplifier unit used in a memory device, comprising: first switching means for turning on / off by an enable signal and initiating a system operation during a turn-on operation; Second switching means for performing an initial operation of the system by performing on / off operations according to voltage states of data held in two data lines in a state that the first switching means is turned on; Third switching means which is turned on by the precharge signal and initializes the potentials of the two output signals; Latch means for latching data input through the second switching means according to the operation of the third switching means and outputting the data to two data output terminals; And a data line connected to one of the data output terminal and the data line of the latch means and being turned on / off according to a voltage state of the other data output terminal, And a feedback switching means for pulling up the potential difference of the latch type sense amplification unit. 1. A sense amplifier unit used in a memory device, comprising: first switching means for on / off operation by an enable signal to initiate system operation during a turn-on operation; Second switching means for performing an initial operation of the system by performing on / off operations according to voltage states of data held in two data lines in a state that the first switching means is turned on; Third switching means which is turned on by the precharge signal and initializes the potentials of the two output signals; Latch means for latching data input through the second switching means according to the operation of the third switching means and outputting the data to two data output terminals; And a potential difference between a bit line connected to the corresponding data line and a data line connected to the data output terminal of the latch unit and the data line and being turned on and off according to an external control signal, And a feedback switching means for pulling up the latch type sense amplifier. The latch type sense amplifier unit according to claim 2, wherein the control signal for on / off operation of the feedback switching means uses the output signal of the delay circuit. A plurality of memory cells for storing data values opposite to each other and outputting data stored in accordance with a voltage state of a word line according to a specified row address combination through a bit line and a plurality of memory cells connected in parallel to a bit line connected to the memory cell A bit line precharge section for precharging and equalizing the bit line by a control signal and a second column select signal controlled by a first column select signal and a second column select signal having a phase opposite to that of the first column select signal, A data line precharge section connected in parallel to the data line connected to the column selection section and for equalizing and equalizing the data line by a control signal, And a sense amplifying unit for receiving and amplifying the data input through the input terminal Wherein the sense amplification unit is connected to either one of the data output terminal and the data line and is turned on / off by an arbitrary control signal which senses that a potential difference of a bit line connected to the data line is out of a predetermined range or more, And a feedback switching means for pulling up the potential of the bit line connected to the data line by a potential applied to the corresponding data output terminal in an on operation, the bit line precharger comprising: a first column selection And a switching means for pulling up the corresponding bit line with a predetermined positive voltage in an on operation, wherein the bit line precharge portion includes a word line, And is configured to have a very large equivalent resistance so as to be discharged. Read circuit of memory. ※ Note: It is disclosed by the contents of the first application.