JP2976195B2 - Latch type sense amplifier and memory read circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier used in a memory device and a memory read circuit having the sense amplifier. In particular, a potential difference between a pair of bit lines is required when a conventional latch-type sense amplifier is applied. In order to prevent the above phenomenon from occurring, the present invention relates to a latch type sense amplifier having negative feedback means for connecting an output of a sense amplifier and a bit line after being enabled.

[0002]

2. Description of the Related Art In general, a sense amplifier is a circuit which detects a voltage or current level of an input signal to a critical value and then amplifies and outputs the same. Further, only a specific time domain input signal is detected. It is sometimes referred to as including the function of performing Such a sense amplifier is generally used for a small output signal output from a storage device or the like.

A sense amplifier used in a memory device is typically of the latch type described above. As an example of the latch type, a current drive type latch type sense amplifier will be described with reference to FIG. It is. FIG. 5 is a circuit diagram of a conventional latch-type sensing and amplifying unit, which is configured as follows.

[0004] Third and fourth PMOSs (MP3, MP4)
Receives an input of a predetermined positive voltage VCC at a source terminal, and turns on / off by a precharge signal SAEQ applied to a gate terminal. The first PMOS (MP1) receives the input of the positive voltage VCC at a source terminal thereof, and
The voltage applied to the drain terminal of the MOS (MP3) is received by the gate terminal to perform on / off operation, and the drain terminal is connected to the drain terminal of the fourth PMOS (MP4).

The second PMOS (MP2) is connected to the positive voltage V
The input of CC is received at the source terminal, and the fourth PMOS (M
The gate terminal receives a voltage applied to the common drain terminal of the first PMOS (MP4) and the first PMOS (MP1) to perform an on / off operation, and the drain terminal is connected to the drain terminal of the third PMOS (MP3). The fourth NMOS (MN4) has a drain terminal connected to the common drain terminal of the fourth PMOS (MP4) and the first PMOS (MP1), and has a gate connected to the common drain terminal of the third PMOS (MP3) and the second PMOS (MP2). Terminal is connected.

The fifth NMOS (MN5) is connected to the third PM (MN5).
A drain terminal is connected to a common drain terminal of the OS (MP3) and the second PMOS (MP2).
A gate terminal is connected to a common drain terminal of the OS (MP4) and the first PMOS (MP1). Second NMOS (
MN2) has a drain terminal connected to the source terminal of the fourth NMOS (MN4), and performs on / off operation according to the data state on the first data line DATA connected to the gate terminal.

The third NMOS (MN3) is connected to the fifth NM.
The drain terminal is connected to the source terminal of OS (MN5), and is turned on / off according to the data state on the second data line DATAB connected to the gate terminal.
It turns off, and the source terminal is the second NMOS (MN2).
Connected to the source terminal. First NMOS (MN
1) has a drain terminal connected to a common source terminal of the second and third NMOSs (MN2, MN3), and is turned on / off by an enable signal SAC flowing into a gate terminal.
Operate off.

The sense amplifier configured as described above is an example of a latch type, and is called a current drive type latch sense amplifier. The operation of each component will be described below. The first NMOS (MN1) is turned on / off by an enable signal SAC, and is a means for starting the operation of the sense amplifier when turning on. Also, the second NMOS
(MN2) and the third NMOS (MN3) are connected to the data line D
This is a means for performing an initial operation of the sense amplifier using data read from a memory cell (not shown) through ATA and DATAB as an input. In addition, the fourth and fifth NMOSs (MN
4, MN5) and the first and second PMOSs (MP1, MP2) are latch units, and the third and fourth PMOSs (MP3, MP4)
Is turned on by the precharge signal SEAQ,
This is a means for initializing the potentials of the output signals SOUT and SOUTB.

A memory readout circuit using a conventional sense amplifier performing the above function will be described with reference to FIG. Memory cell 50
Stores a conflicting data value, selects a word line WL according to a specified row address combination, and outputs the stored data through bit lines BIT and BITB according to the voltage state of the selected word line WL. .

The bit line precharge unit 40 is connected to the bit lines BIT, BIT,
The bit lines BIT and BITB are pre-charged and equalized by a control signal DTEQ in parallel with BITB. The column selection unit 30 is controlled by a first column selection signal YSW and a second column selection signal YSWB having an opposite phase to the first column selection signal YSW.
T and BITB are connected to the data lines DATA and DATAB.

The data line precharge unit 20 includes a data line DAT connected to the column selection unit 30.
A, DATAB and the control signal CDE
The Q precharges and equalizes the data lines DATA and DATAB. Sensing amplifier 10
Receives data input through the data lines DATA and DATAB, amplifies the data, and outputs the amplified data.

Although FIG. 6 shows one memory cell 50, a plurality of memory cells having the same configuration are provided in parallel on the bit lines BIT and BITB. Since the configuration of the memory read circuit as described above is general,
Detailed description of each component will be omitted, and the operation characteristics of each component of the memory read circuit will be considered below. When the word line WL is selected by the designated row address combination and the bit line is selected by the column address combination, that is, the first column selection signal YSW is in the high state,
When the second column selection signal YSWB is in the low state, the data stored in the memory cell 50 is changed to the bit lines BIT, BITB and the data lines DATA, DAT.
The signal enters the input terminal of the sense amplifier 10 through AB.

The bit line precharge unit 40 not described in the above description is for precharging the potential levels of the bit lines BIT and BITB before the selected word line is enabled. That is, the PMOS (which constitutes the bit line precharge unit 40)
MP21 to MP25), the PMOS (MP21, M
P22) performs a function of pulling up the bit lines BIT and BITB to a predetermined positive voltage VCC level,
S (MP25) performs an equalizing function to make the potentials of the bit lines BIT and BITB the same. In addition, PMOS (MP
23, MP24) is a bit line BIT in a static state,
The level of BITB is maintained at the positive voltage VCC, and the bit lines BIT, BIT,
It prevents the potential difference of BITB from becoming excessively large.

The role of the data line precharge unit 20 is the same as that of the precharge unit 40 described above, and the PMOS (MP1
The functions of the bit line precharge unit 40 are denoted by reference numerals MP25 and MP25, respectively.
This corresponds to the circuit configuration of P21 and MP22.

[0015]

Although the operation of the memory read circuit has been roughly considered above, the role and problems of the sense amplifier used in the conventional memory read circuit operating as described above will be described with reference to the above configuration. This will be described in detail with reference to FIG. Considering the input state before the sense amplifier 10 is enabled, the data lines DATA and DATAB are precharged to the level of the positive voltage VCC, and the enable signal SAC and the precharge signal SEAQ are in a low state (see FIG. 7C). It is in. Thereby, the first NMOS (M
N1) is disabled, the path through which the output node can be discharged is cut off, and the third PMOS (M
Since P3) and the fourth PMOS (MP4) are turned on, the potentials of the outputs SOUT and SOUTB on both sides are raised to the level of the positive voltage VCC.

Thereafter, when the word line and the column are opened and the precharging of the bit line and the data line is completed, that is, the control signal CD inputted to the precharge units 20 and 40 for precharging the data line and the bit line.
EQ and DTEQ all transition to high state (see Fig. 7B)
Then, while the potential of the portion of the two bit lines connected to the low node of the memory cell 50 is lowered, a potential difference between the bit line pair starts to occur.

After a certain time delay, the enable signal SAC and the precharge signal SAEQ change to high, the precharge of the sense amplifier 10 is completed, and the sensing function for the input potential difference is started (see FIG. 7C). The minimum potential difference dV1 (see FIG. 7D) of the bit line pair that prevents the sense amplifier 10 from malfunctioning is an offset voltage Voffset generated by an asymmetric element of the sense amplifier 10.
Is the same as

The second NMOS (MN2) used as an input terminal and the third NMO
S (MN3) converts a potential difference between the data lines DATA and DATAB into a current difference. At this time, the discharge speed of the output unit differs depending on the converted current difference, and thus a potential difference occurs at both nodes of the output unit. Also, NMO
The latch section composed of S (MN4, MN5) and PMOS (MP1, MP2) increases the potential difference of the output section so that the output section is latched at a high speed.

When the potential of the first data line DATA is higher than the potential of the second data line DATAB, the first output signal SOUT is latched high and the second output signal SOU is output.
TB is latched low. Once latched, the first
The output signal SOUT is continuously maintained at a high level by the second PMOS (MP2), and the fifth NMOS (MN5).
Is turned off. Conversely, the second output signal SOU
TB is the first, second, and fourth NMOSs (MN1, MN2, M
N4) holds the low state, and the first PMOS (M
P1) is turned off.

After the sensing and amplifying unit 10 is latched, even if the potential difference between the data lines DATA and DATAB is changed or further inverted, the once latched state remains unchanged. Therefore, there is an advantage that operation stability can be ensured by using such a latch-type sense amplifier. On the other hand, if the sense amplification unit 10 has asymmetry, a potential difference enough to offset the offset voltage due to the asymmetry should be applied to the input terminal. Means that the sense amplifier should be enabled after the potential difference is generated.

In order to reduce the time delay, the equivalent resistance of the PMOSs (MP23, MP24) performing the DC pull-up function in the configuration of the bit line precharge unit 40 should be increased. However, as shown in FIG. 7, even after the sensing and amplifying unit 10 is latched, the potential difference between the bit line pair continues to increase and becomes saturated at the value of dV2 (see FIG. 7D). This value is determined by the ratio between the current driving force of the memory cell and the current driving force of the DC pull-up.

However, when the address is changed and the read operation for the data of another memory cell is started, the smaller the value of dV2, the better the precharge of the bit line is. For this purpose, the equivalent resistance of the DC pull-up must be small. Therefore, as described above, it is necessary to increase the equivalent resistance of the DC pull-up in order to reduce the time delay associated with the enable of the sense amplifier, and to increase the pre-charge speed during address translation. There is a considerable bottleneck in the design, as conflicting requirements arise that the up equivalent resistance must be reduced.

The present invention has been made to solve the above-mentioned conventional problems. A first object of the present invention is to provide a negative feedback means, and after the latch-type sense amplifier is enabled, the negative feedback means is provided. It is an object of the present invention to provide a latch-type sense amplifier that prevents the potential difference between a pair of bit lines from becoming unnecessarily large by connecting an output of the sense amplifier to a bit line.

A second object of the present invention is to provide a memory read circuit to which a latch type sense amplifier having the negative field-back means can be applied.

[0025]

According to a first aspect of the present invention, there is provided a sense amplifier used in a memory device, which is turned on / off by an enable signal.
A first switching means for performing an off operation and initializing a system operation at the time of a turn-on operation, and an on / off state according to a state of a data voltage applied to the two data lines when the first switching means is turned on.
A second switching means for performing an initial operation of the system by performing an off operation; a third switching means for being turned on by a precharge signal to initialize the potentials of two output signals; and a second switching means for performing an operation of the third switching means. 2
A latch means for latching data flowing in through the switching means and outputting the data to two data output terminals, and each of which is connected between each data output terminal of the latch means and each of the data lines; Feedback switching means for performing on / off operation according to the voltage state of the output terminal and pulling up the potential of the low potential side bit line connected to the data line with the potential applied to the data output terminal during the on operation; It is characterized by including.

According to the first aspect of the present invention, when the output is latched by the enable signal, one data output terminal is maintained in a high state and the other data output terminal is maintained in a low state. Also, the feedback switching means connected to the one data output terminal is turned on according to the low state voltage of the other data output terminal.

Thus, the potential of one of the data output terminals in the high state changes the potential of the lower potential bit line connected to the data line via the data line connected to the data output terminal. It is pulled up and the potential difference with the other bit line is reduced. Therefore, the effect of reducing the bit line precharge time during address conversion can be obtained.

According to another aspect of the present invention, there is provided a sense amplifier used in a memory device, which is turned on / off by an enable signal and initializes a system operation at a turn-on operation. First
Switching means; second switching means for performing an initial operation of the system by performing on / off operations in accordance with a voltage state of data carried on the two data lines in a state where the first switching means is turned on; A third switching unit that is turned on by the signal and initializes the potentials of the two output signals; and, according to the operation of the third switching unit, latches data flowing through the second switching unit to perform two data output terminals. Connected to each data output terminal of the latch means and each of the data lines, and are turned on / off in response to an external control signal and are connected to the data output terminals during the on operation. With this potential, the potential of the bit line on the low potential side connected to the data line is pulled out. Characterized in that it comprises a feedback switching means for up and.

According to the second aspect of the present invention, the output is latched by the enable signal in the same manner as described above, and one of the data output terminals is maintained in a high state, and the other data output terminal is maintained in a low state. Feedback switching means connected to the data output terminal is turned on in response to the external control signal.

Thus, the potential of one of the data output terminals in the high state changes the potential of the lower potential bit line connected to the data line via the data line connected to the data output terminal. It is pulled up and the potential difference with the other bit line is reduced. Therefore, the effect of reducing the bit line precharge time during address conversion can be obtained.

According to a third aspect of the present invention, in the second aspect of the present invention, the control signal for the on / off operation of the feedback switching means uses an output signal of a delay circuit. . According to the third aspect of the present invention, since the output terminal of the sense amplifier and the data line can be kept in the cutoff state by the control signal delayed by the delay circuit, the latch operation can be further speeded up. In order to achieve the second object of the present invention,
The invention according to claim 4 stores the conflicting data values, selects a word line according to a specified row address combination, and stores the stored data through a bit line according to the voltage state of the selected word line. A plurality of memory cells to be output, and a bit line precharge unit which is connected in parallel to a bit line connected to the memory cell, and precharges and equalizes the bit line by a control signal, A column selection unit that is controlled by a first column selection signal and a second column selection signal having an opposite phase and is connected to the bit line and the data line, and is connected to a data line connected to the column selection unit. And a data line for precharging and equalizing the data line by a control signal. In a memory read circuit including a precharge unit and a sense amplification unit that receives data input flowing through the data line, amplifies and outputs the data, the sense amplification unit includes a data output terminal and a data line. On / off operation is performed by an arbitrary control signal that senses that the potential difference between the bit line connected to the data line and the bit line connected to the data line is out of a predetermined range. A feedback switching unit for pulling up a potential of a bit line connected to the line, wherein the bit line precharge unit performs on / off operation according to a first column selection signal input to the column selection unit; Switching for pulling up the bit line with a predetermined positive voltage during ON operation Equipped with a stage, and,
After the word line is selected, the low nodes of the pair of bit lines are configured to have a large equivalent resistance so as to be discharged quickly.

According to the fourth aspect of the present invention, since the sense amplifier has the same feedback switching means as the invention related to the sense amplifier, the potential of the low potential side bit line is pulled up, The effect that the potential difference from the other bit line is reduced and the bit line precharge time during address conversion is reduced is similarly obtained.

Also, the bit line precharge unit has an increased equivalent resistance as compared with the conventional case, so that the low nodes of the bit line pair are discharged quickly after the word line is selected. It is possible,
It is possible to reduce a delay time until the potential difference of the input part of the sense amplifier reaches the offset voltage. In addition, when a column is selected, a read operation is performed by a switching means of a bit line precharge unit controlled by the first column selection signal, and when a column is not selected, a corresponding positive voltage is applied by a predetermined positive voltage. By pulling up the line, the potential difference between the bit line pair can be kept at a small value.

[0034]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a circuit diagram of a latch-type sense amplifier according to the present invention, which is configured as follows. Third and fourth PMOSs (MP10
3, MP104) receives an input of a predetermined positive voltage VCC at a source terminal, and turns on / off according to a precharge signal SEAQ applied to a gate terminal.

The first PMOS (MP101) receives the input of the positive voltage VCC at a source terminal and receives the third PMOS (MP101).
(MP103) receives on the gate terminal a voltage applied to the drain terminal, and performs an on / off operation.
It is connected to the drain terminal of the PMOS (MP104). The second PMOS (MP102) is connected to the positive voltage VCC.
Is input to the source terminal, and the fourth PMOS (MP1
04) and the voltage applied to the common drain terminal of the first PMOS (MP101) is received by the gate terminal to perform on / off operation, and the drain terminal is connected to the drain terminal of the third PMOS (MP103).

The fourth NMOS (MN104) is connected to the fourth NMOS (MN104).
PMOS (MP104) and first PMOS (MP101)
The drain terminal is connected to the common drain terminal of
The third PMOS (MP103) and the second PMOS (MP103)
102), the gate terminal is connected to the common drain terminal. The fifth NMOS (MN105) is connected to the third PMO
A drain terminal is connected to a common drain terminal of the S (MP103) and the second PMOS (MP102), and the fourth PMOS (MP104) and the first PMOS (MP10) are connected.
The gate terminal is connected to the common drain terminal of 1).

The second NMOS (MN102) is connected to the fourth NMOS (MN102).
The drain terminal is connected to the source terminal of the NMOS (MN104), and the NMOS (MN104) performs an on / off operation according to the data state loaded on the first data line DATA connected to the gate terminal. The third NMOS (MN103) is
A drain terminal is connected to a source terminal of the fifth NMOS (MN105), and the fifth NMOS (MN105) is turned on / off according to a data state on a second data line DATAB connected to a gate terminal. 2nd N
It is connected to the source terminal of the MOS (MN102).

The first NMOS (MN101) has a drain terminal connected to the common source terminal of the second and third NMOSs (MN102, 103), and is turned on / off by an enable signal SAC flowing into the gate terminal. The fifth PMOS (MP105) is composed of the first PMOS (MP101) used as a second output terminal and the fourth PM (MP105).
A source terminal is connected to a common drain terminal of the OS (MP104), and a signal applied to a gate terminal of the fourth NMOS (MN104) is received at the gate terminal to perform on / off operation. (MN1
02) outputs the potential supplied to the source terminal to the connected drain terminal of the first data line DATA connected to the gate terminal.

The sixth PMOS (MP106) has a source terminal connected to the common drain terminal of the second PMOS (MP102) and the third PMOS (MP103) used as the first output terminal, and has a fifth NMOS (MN105).
Receiving an input of a signal applied to the gate terminal of the third NMOS transistor to perform an on / off operation;
The potential supplied to the source terminal is output to the drain terminal connected to the second data line DATAB connected to the gate terminal of (MN103).

The difference between the structure of the sense amplifier according to the present invention shown in FIG. 4 and the structure of the prior art sense amplifier shown in FIG. Means MP105 and MP106 for connecting a data line to the device and performing a feedback function. FIG. 2 shows a memory read circuit according to the present invention configured using the sense amplifier.

When comparing the memory read circuit according to the present invention shown in FIG. 2 with the conventional memory read circuit shown in FIG. 6, the difference in structure is that the bit line precharge unit 40A has Turned on in response to the first column selection signal YSW of the column selection unit 30A, and a predetermined positive voltage V
PMOS (M) that precharges a bit line to CC
P126, MP127) are added.

Since the basic operations of the sense amplifier and the memory read circuit shown in FIGS. 1 and 2 are the same as those of the circuits shown in FIGS. The description will be omitted, and only the operation of the circuit according to the present invention corresponding to the conventional problem will be described in detail with reference to FIG. When the sense amplifier 10A is in the precharge state, the fifth PMO
The S (MP105) and the sixth PMOS (MP106) are turned off.

When the sense amplifier 10A is enabled and the output is latched, the fifth PMOS (MP10) is activated.
Either 5) or the sixth PMOS (MP106) is turned on. Here, the potential of the first data line DATA is higher than the potential of the second data line DATAB, the first output signal SOUT is in a high state, and the second output signal S
Taking the case where OUBT is in a low state as an example, the fifth
The PMOS (MP105) is turned off and the sixth PMOS
S (MP106) is turned on.

Thus, the second PMOS (MP102)
And the current flowing through the sixth PMOS (MP106) charges the second data line DATAB and raises the potential level of the second data line DATAB, so that the potential difference between the first data line DATA and the second data line DATAB decreases and the bit line Potential difference (see dV5 in FIG. 2D)
Decrease as well.

Therefore, the effect of reducing the bit line precharge time during address conversion can be obtained. In the memory read circuit proposed to utilize the negative feedback characteristic of the sense amplifier 10A as described above, the DC pull-up function of the PMOS (MP121 to MP127) constituting the bit line precharge unit 30A is used. (MP123, MP124)
Has a higher equivalent resistance than the conventional case, and the low nodes of the bit line pair can be discharged faster after the word line is selected.

Therefore, it is possible to reduce the delay time until the potential difference at the input of the sensing circuit reaches the offset voltage (see dV3 in FIG. 2D). In some cases, the bit line may be designed so that the DC pull-up (MP123, MP124) is omitted. As described above, the potential difference of the bit line of the selected column is reduced by the feedback means of the sense amplifier. On the other hand, when a word line is selected from an unselected column and the potential difference between the bit line pair becomes large, the equivalent resistance of the DC pull-up is very large, and it is necessary to prevent the potential difference from becoming excessive. .

In order to achieve this object, bit line pull-up means (MP126, MP127) controlled by the first column selection signal YSW are added. When a column is selected, the PMOS (MP126,
MP127) is in the turn-off state, so that the read operation is performed as described above. On the other hand, if a column is not selected, the PMOS (MP126, MP127) is turned on. Since the current driving force of the pull-up means is larger than the current driving force of the memory cell, the potential difference between the bit line pair can be kept at a small value.

Therefore, according to the latch-type sense amplifier having the negative feedback means and the memory readout circuit having the amplifier according to the present invention, the conventional memory access circuit is inconsistent at the time of designing. In other words, in order to reduce the time delay associated with enabling the sense amplifier, the equivalent resistance of the DC pull-up must be increased. The effect is obtained that the conflicting requirement that the equivalent resistance of the pull-up must be reduced can be eliminated.

A feature of the configuration of the sense amplifier in the above-described embodiment is that the output signals SOUT and SOUTB of the amplifier are fed back to the data line, and the other output signals SOUTB and SOU are used as control signals for the signals.
The use of T. Unlike such an embodiment, an embodiment in which the control signal is operated by a delay circuit (not shown) is also conceivable.

Although the second embodiment is shown in FIG. 3, the characteristics of the sense amplifier shown in FIG. 3 are sensed by the control signal delayed by the delay circuit before the latch operation is completed. Since the output terminal of the amplifying unit and the data line can be kept in the cut-off state, the latch operation can be made faster than in the circuit of the first embodiment shown in FIG.

On the other hand, in the sense amplifier circuit shown in FIG. 3, the potential difference between the bit lines may increase immediately before the feedback (see dV4 in FIG. 2D). This is a factor that reduces the line precharge speed, and in this regard, the first embodiment is superior. However, in the second embodiment, dV4, which is the increase in the potential difference between the bit lines immediately before the feedback, is smaller than the maximum bitline potential difference (see dV2 in FIG. 7D). A clear effect can be obtained in comparison.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a latch-type sense amplifier according to the present invention.

FIG. 2 is a circuit diagram of a memory read circuit using the sense amplifier shown in FIG. 1;

FIG. 3 is an exemplary operation waveform diagram of a main part when the circuit of FIG. 2 operates.

FIG. 4 is a diagram of another embodiment of a latch-type sense amplifier according to the present invention.

FIG. 5 is a circuit configuration diagram of a conventional latch-type sense amplifier.

FIG. 6 is a circuit diagram of a memory read circuit using the sense amplifier shown in FIG. 5;

FIG. 7 is an exemplary diagram of an operation waveform of a main part during the operation of the second circuit.

[Explanation of symbols]

 MP101 1st PMOS MP102 2nd PMOS MP103 3rd PMOS MP104 4th PMOS MP105 5th PMOS MP106 6th PMOS MN101 1st NMOS MN102 2nd NMOS MN103 3rd NMOS MN104 4th NMOS MN105 5th NMOS 10A Sense amplification unit 30A Column selection unit 40A Bit line pre-charger 40A Data line DATAB Second data line

Claims (4)

(57) [Claims] 1. A sensing and amplifying unit used in a memory device, comprising: a first switching unit for performing an on / off operation according to an enable signal to initialize a system operation during a turn-on operation; and a state in which the first switching unit is turned on. A second switching means for performing an initial operation of the system by performing an on / off operation in accordance with a state of the data voltage applied to the two data lines, and being turned on by a precharge signal to initialize the potentials of the two output signals. A third switching means, a latch means for performing a latch operation to output data flowing through the second switching means in response to the operation of the third switching means, and outputting the data to two data output terminals, Connected between an output terminal and each of the data lines, Feedback switching in which the on / off operation is performed in accordance with the voltage state of the other data output terminal and the potential of the low potential side bit line connected to the data line is pulled up by the potential applied to the data output terminal during the on operation. Means, and a latch-type sense amplifier. 2. A sensing and amplifying unit used in a memory device, comprising: a first switching unit that is turned on / off by an enable signal and initializes a system operation at the time of a turn-on operation; and a state in which the first switching unit is turned on. A second switching means for performing an initial operation of the system by performing an on / off operation according to a voltage state of data carried on the two data lines, and turning on a precharge signal to initialize the potentials of the two output signals. Third switching means, data means for latching data flowing through the second switching means in response to the operation of the third switching means and outputting the data to two data output terminals, and each data output terminal of the latch means And each of the data lines are connected between the Feedback switching means for performing an on / off operation in response to a control signal and pulling up a potential of a lower potential bit line connected to the data line with a potential applied to the data output terminal during the on operation. A latch-type sense amplifier. 3. The latch-type sense amplifier according to claim 2, wherein an output signal of a delay circuit is used as a control signal for turning on / off the feedback switching means. 4. A method for storing conflicting data values, selecting a word line according to a specified row address combination, and outputting stored data through a bit line according to a voltage state of the selected word line. A plurality of memory cells, a bit line precharge unit connected in parallel to the bit lines connected to the memory cells, for precharging and equalizing the bit lines by a control signal, and a first column. The bit line is controlled by a selection signal and a second column selection signal having the opposite phase, and is connected to a column selection unit for connecting the bit line and the data line, and to a data line connected to the column selection unit. , A data line precharger for precharging and equalizing the data line by a control signal. A memory readout circuit comprising: a sense amplifier for receiving and amplifying and receiving data input through the data line, wherein the sense amplifier has a data output terminal and a data line, respectively. The ON / OFF operation is performed by an arbitrary control signal that is detected that the potential difference between the connected bit line and the data line is out of a predetermined range, and the potential applied to the data output terminal during the ON operation is set to the data line. And a feedback switching means for pulling up a potential of a bit line connected to the bit line, wherein the bit line precharge unit is turned on / off in response to a first column selection signal input to the column selection unit. Switching means for pulling up the bit line with a predetermined positive voltage during operation; And a memory read circuit configured to have a large equivalent resistance so that a low node of a bit line pair is quickly discharged after a word line is selected.