KR980007901A - Lamination method of multilayer printed circuit board capable of shortening process - Google Patents

Lamination method of multilayer printed circuit board capable of shortening process Download PDF

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Publication number
KR980007901A
KR980007901A KR1019960024636A KR19960024636A KR980007901A KR 980007901 A KR980007901 A KR 980007901A KR 1019960024636 A KR1019960024636 A KR 1019960024636A KR 19960024636 A KR19960024636 A KR 19960024636A KR 980007901 A KR980007901 A KR 980007901A
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KR
South Korea
Prior art keywords
printed circuit
circuit board
multilayer printed
manufacturing
stacking
Prior art date
Application number
KR1019960024636A
Other languages
Korean (ko)
Other versions
KR100206377B1 (en
Inventor
양덕진
박수진
Original Assignee
이형도
삼성전기주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 이형도, 삼성전기주식회사 filed Critical 이형도
Priority to KR1019960024636A priority Critical patent/KR100206377B1/en
Publication of KR980007901A publication Critical patent/KR980007901A/en
Application granted granted Critical
Publication of KR100206377B1 publication Critical patent/KR100206377B1/en

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

본 발명은 컴퓨터, 가전제품 등에 사용되는 다층인쇄회로기판(multi-layer printed circurd board)의 제조방법에 관한 것이며, 그 목적은 다층인쇄회로기판의 제조시 기존의 핀방식에서 필요로 하는 세부 추가설비 등이 필요치 않을 뿐만아니라 무엇보다도 적충공정이 크게 단축되고 간편하고 신속한 적층작업이 이루어지도록 함에 있다. 상기 목적달성을 위한 본 발명은 다층인쇄회로기판의 제조방법에 있어서, 하측으로부터 프리플랙, 동박적층판(CCL) 및 프리플랙의 순서로 프리플랙과 동박적층판을 순차적으로 적치한 후, 적치된 적층기판을 리베팅하고 리벳으로 고정된 적층기판의 상하 양측에 다시 동박을 위치시키는 예비적층단계; 상기와 같은 여러번의 예비적층공정을 통해 다수의 적층기판을 마련하는 단계; 및 상기 예비적층된 각 적층기판을 이송하는 캐리어판에 하측으로부터 쿠션지, 지지판 및 다수개의 예비적층기판을 적치한 다음, 다시 쿠션지 및 지지판을 올려놓고 그 최상부에는 카바를 적치하는 단계; 를 포함하여 구성되는 공정단축이 가능한 다층인쇄회로기판의 적층방법에 관한 것을 그 기술적 요지로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multi-layer printed circuit board used in a computer, a home appliance, and the like, and its object is to provide a method of manufacturing a multilayer printed circuit board, And besides, the laminating process is greatly shortened, and the laminating operation is carried out in a simple and quick manner. In order to achieve the above object, the present invention provides a method of manufacturing a multilayer printed circuit board, comprising: sequentially stacking a pre-flake and a copper-clad laminate in the order of a pre-flake, a CCL, and a pre- A preliminary lamination step of placing the copper foil again on both upper and lower sides of the laminated board fixed by riveting and riveting; Providing a plurality of laminated substrates through the preliminary lamination process as described above; A step of stacking a cushion paper, a support plate and a plurality of preliminary laminated boards from a lower side on a carrier plate for conveying the preliminarily stacked laminated boards, placing the cushion paper and the support plate thereon, The present invention relates to a method of stacking a multilayer printed circuit board capable of shortening the manufacturing process.

Description

공정단축이 가능한 다층인쇄회로기판의 적층방법Lamination method of multilayer printed circuit board capable of shortening process

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명의 리벳방식을 이용한 다층인쇄회로기판의 적층과정을 나타내는 모식도.FIG. 2 is a schematic view showing a lamination process of a multilayer printed circuit board using the rivet method of the present invention. FIG.

Claims (2)

다층인쇄회로기판의 제조방법에 있어서, 하측으로부터 프리플랙, 동박저층판 (CCL) 및 프리플랙의 순서로 프리플랙과 동박적층판을 순차적으로 적치한 후, 이를 리베팅하고 고정된 적층기판의 상하 양측에 다시 동박을 위치시키는 예비적층단계; 상기와 같은 여러번의 예비적층공정을 통해 다수의 적층기판을 마련하는 단계; 및 상기 예비적층된 각 적층기판을 이송하는 캐리어판에 하측으로부터 쿠션지, 지지판 및 다수개의 예비적층기판을 적치한 다음, 다시 쿠션지 및 지지판을 올려놓고 그 최상부에는 카바를 적치하는 단계; 를 포함하여 구성됨을 특징으로 하는 공정단축이 가능한 다층인쇄회로기판의 적층방법.A method of manufacturing a multilayer printed circuit board, comprising the steps of sequentially stacking a pre-flake and a copper-clad laminate in the order of pre-flake, CCL and pre-flake from the bottom, A preliminary lamination step of placing the copper foil again on the copper foil; Providing a plurality of laminated substrates through the preliminary lamination process as described above; A step of stacking a cushion paper, a support plate and a plurality of preliminary laminated boards from a lower side on a carrier plate for conveying the preliminarily stacked laminated boards, placing the cushion paper and the support plate thereon, Wherein the step of stacking the multilayer printed circuit boards comprises: 제1항에 있어서, 상기 예비적층된 적층기판은 6층이상의 인쇄회로기판임을 특징으로 하는 적층방법.The method of claim 1, wherein the pre-laminated substrate is a printed circuit board having six or more layers.
KR1019960024636A 1996-06-27 1996-06-27 Lay up method of multi-layer printed circuit board capable of reducing fabricating process KR100206377B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960024636A KR100206377B1 (en) 1996-06-27 1996-06-27 Lay up method of multi-layer printed circuit board capable of reducing fabricating process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960024636A KR100206377B1 (en) 1996-06-27 1996-06-27 Lay up method of multi-layer printed circuit board capable of reducing fabricating process

Publications (2)

Publication Number Publication Date
KR980007901A true KR980007901A (en) 1998-03-30
KR100206377B1 KR100206377B1 (en) 1999-07-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960024636A KR100206377B1 (en) 1996-06-27 1996-06-27 Lay up method of multi-layer printed circuit board capable of reducing fabricating process

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030010312A (en) * 2001-07-26 2003-02-05 삼성전기주식회사 Method for preparing multilayer package substrate using the rivet

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030048283A (en) * 2001-12-11 2003-06-19 파이어니어 테크놀로지 엔지니어링 컴퍼니 리미티드 Method for manufacturing a copper-clad laminate
KR20030048281A (en) * 2001-12-11 2003-06-19 파이어니어 테크놀로지 엔지니어링 컴퍼니 리미티드 Method for manufacturing a copper-clad laminate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030010312A (en) * 2001-07-26 2003-02-05 삼성전기주식회사 Method for preparing multilayer package substrate using the rivet

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KR100206377B1 (en) 1999-07-01

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