KR980006523A - Bipolar semiconductor device and manufacturing method thereof - Google Patents

Bipolar semiconductor device and manufacturing method thereof Download PDF

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KR980006523A
KR980006523A KR1019960038940A KR19960038940A KR980006523A KR 980006523 A KR980006523 A KR 980006523A KR 1019960038940 A KR1019960038940 A KR 1019960038940A KR 19960038940 A KR19960038940 A KR 19960038940A KR 980006523 A KR980006523 A KR 980006523A
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conductivity type
transistor
impurity concentration
epitaxial layer
well region
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KR100272636B1 (en
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마사아키 이케가미
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기다오까 다까시
미쓰비시 뎅끼 가부시끼가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8228—Complementary devices, e.g. complementary transistors
    • H01L21/82285—Complementary vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
    • H01L27/0826—Combination of vertical complementary transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

콜렉터와 베이스사이의 용량을 작게하고 응답속도를 가속하여 높은 CB 접합내압(BVCBO)을 가지는 본 발명에 의해 제조된 바이폴라 반도체 장치.A bipolar semiconductor device manufactured by the present invention having a high CB junction breakdown voltage (BVCBO) by reducing the capacitance between the collector and the base and accelerating the response speed.

종형 트랜지스터의 베이스가 되는 A n+형 웰확산층(105)은 p+형 매립영역에 도달하도록 형성된다.The A n + type well diffusion layer 105 serving as the base of the vertical transistor is formed to reach the p + type buried region.

나아가, a p+형 확산층(106)은 p+형 매립영역에 도달하고 형성되고 소정의 거리(d)의 간격에서 n+형 매립 확산층(4)을 둘러싸도록 형성된다.Furthermore, a p + type diffusion layer 106 is formed to reach and form a p + type buried region and surround the n + type buried diffusion layer 4 at intervals of a predetermined distance d.

NA(104) X ND(105)곱은 NA(106) X ND(102)곱 보다 크게 고정되며, 상기에서 NA(104)는 콜렉터가 되는 상기 제1 전도형 매립층의 불순물농도이고; NA(106)는 콜렉터전극이 되는 상기확산영역의 불순물농도이고; ND(102)는 상기 제2 전도형 에피택셜층의 불순물농도이고; ND(105)는 트랜지스터용 베이스가 되는 상기 제2 전도형 웰영역의 불순물 농도이다.The NA 104 X ND 105 product is fixed to be larger than the NA 106 X ND 102 product, where NA 104 is the impurity concentration of the first conductivity type buried layer that becomes the collector; NA 106 is an impurity concentration of the diffusion region serving as a collector electrode; ND 102 is an impurity concentration of the second conductivity type epitaxial layer; ND 105 is an impurity concentration of the second conductivity type well region serving as a transistor base.

Description

바이폴라 반도체 장치 및 그 제조방법Bipolar semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 제1실시예에 따른 단면도.1 is a cross-sectional view according to a first embodiment of the present invention.

Claims (7)

바이폴라 반도체 장치는Bipolar semiconductor device (1) 제1 전도형의 반도체 기판과;(1) a semiconductor substrate of a first conductivity type; (2) 상기 반도체 기판위에 형성된 제2 전도형의 에피택셜층들과;(2) second epitaxial layers formed on the semiconductor substrate; (3) 에피택셜층과 반도체 기판 사이에 형성된 상기 제2 전도형의 매립층들과;(3) said buried layers of said second conductivity type formed between an epitaxial layer and a semiconductor substrate; (4)상기 제2 전도형의 상기 매립층중에 형성된 트랜지스터의 콜렉터가 있는 상기 제1 전도형의 매립층들과;(4) buried layers of the first conductivity type having collectors of transistors formed in the buried layers of the second conductivity type; (5) 상기 애피택셜층의 일부에서 형성되고 상기 애피택셜층보다 불순물 농도가 더 높게 제공된 트랜지스터의 베이스가 있는 상기 제2 전도형의 웰영역들과;(5) well regions of the second conductivity type having a base of a transistor formed in a portion of the epitaxial layer and provided with a higher impurity concentration than the epitaxial layer; (6) 상기 제1 전도형의 상기 매립층위에 형성된 트랜지스터의 콜렉터의 전극이 있는 상기 제1 전도형의 확산영역들과;(6) diffusion regions of the first conductivity type having electrodes of collectors of transistors formed on the buried layer of the first conductivity type; (7) 상기 웰영역에 형성된 트랜지스터의 에미터가 있는 상기 제1 전도형의 확산영역들을 구비하고, 상기 트랜지스터의 콜렉터가 있는 상기 제1 전도형의 상기 매립층과 접속하고 트랜지스터의 수평방향에서 간격(d)는 상기 웰영역의 상기 에피택셜층을 통하여 상기 트랜지스터의 콜렉터 전극이 있는 상기 확산영역을 둘러싸여 있고, NA(104) X ND(105) 곱은 NA(106) X ND(102)곱 보다 크게 조정되며, NA(104)는 콜렉터가 되는 상기 제1 전도형 매립층의 불순물농도이고; NA(106)는 콜렉터전극이 되는 상기확산영역의 불순물농도이고; ND(102)는 제2 전도형 에피택셜층의 불순물농도이고; ND(105)는 트랜지스터용 베이스가 되는 상기 제2 전도형 웰영역의 불순물 농도 바이폴라 반도체 장치)(7) a diffusion region of the first conductivity type having an emitter of a transistor formed in the well region, connected to the buried layer of the first conductivity type having a collector of the transistor, and having a spacing in the horizontal direction of the transistor ( d) surrounds the diffusion region with the collector electrode of the transistor through the epitaxial layer of the well region, and the NA 104 X ND 105 product is adjusted to be greater than NA 106 X ND 102 product. NA 104 is an impurity concentration of the first conductivity type buried layer serving as a collector; NA 106 is an impurity concentration of the diffusion region serving as a collector electrode; ND 102 is an impurity concentration of the second conductivity type epitaxial layer; ND 105 is an impurity concentration bipolar semiconductor device of the second conductivity type well region serving as a base for transistors) 제1항에 있어서, 상기 제1 전도형의 상기 확산영역의 일단부터 상기 제2 전도형의 상기 웰영역의 일단까지의 표면위에 형성된 필드산화층들을 구비하는 바이폴라 반도체 장치.The bipolar semiconductor device according to claim 1, further comprising field oxide layers formed on a surface from one end of said diffusion region of said first conductivity type to one end of said well region of said second conductivity type. 제1항 또는 제2항에 있어서, 상기 제2 전도형의 상기 에피택셜층에서 불순물 농도가 2.0*1015cm-3~2.0*1016cm-3인 바이폴라 반도체 장치.The bipolar semiconductor device according to claim 1 or 2, wherein the impurity concentration in the epitaxial layer of the second conductivity type is 2.0 * 10 15 cm -3 to 2.0 * 10 16 cm -3 . 제1항 또는 제2항에 있어서 상기 에피택셜층보다 더 높은 상기 제2 전도형의 상기 웰 영역의 불순물 농도가 2.0*1015cm-3~2.0*1016cm-3인 바이폴라 반도체 장치.The bipolar semiconductor device according to claim 1 or 2, wherein an impurity concentration in the well region of the second conductivity type higher than the epitaxial layer is 2.0 * 10 15 cm -3 to 2.0 * 10 16 cm -3 . 제1항 또는 제2항에 있어서, 상기 제2 전도형의 상기 에피텍셜층의 두께가 0.5㎛~10.0㎛ 이고 상기 제2 전도형의 상기 웰영역의 불순물 확산깊이가 0.5㎛ ~10.0㎛인 바이폴라 반도체 장치.The bipolar of claim 1 or 2, wherein the thickness of the epitaxial layer of the second conductivity type is 0.5 µm to 10.0 µm and the impurity diffusion depth of the well region of the second conductivity type is 0.5 µm to 10.0 µm. Semiconductor device. (1) 제1 전도형의 반도체 기판과;(1) a semiconductor substrate of a first conductivity type; (2) 상기 반도체 기판위에 형성된 제2 전도형의 에피택셜층들과;(2) second epitaxial layers formed on the semiconductor substrate; (3) 상기 에피택셜층과 반도체 기판 사이에 형성된 상기 제2 전도형의 매립층들과;(3) buried layers of the second conductivity type formed between the epitaxial layer and the semiconductor substrate; (4)제2 전도형의 상기 제1 매립층중에 형성된 트랜지스터의 콜렉터가 있는 상기 제1 전도형의 매립층들과;(4) buried layers of the first conductivity type with collectors of transistors formed in the first buried layer of a second conductivity type; (5) 상기 애피택셜층의 일부에서 형성되고 상기 애피택셜층보다 불순물 농도가 더 높게 제공된 트랜지스터의 베이스가 있는 상기 제2 전도형의 웰영역들과;(5) well regions of the second conductivity type having a base of a transistor formed in a portion of the epitaxial layer and provided with a higher impurity concentration than the epitaxial layer; (6) 상기 제1 전도형의 상기 매립층위에 형성된 트랜지스터의 콜렉터의 전극이 있는 상기 제1 전도형의 확산영역들과;(6) diffusion regions of the first conductivity type having electrodes of collectors of transistors formed on the buried layer of the first conductivity type; (7) 상기 웰영역에 형성된 트랜지스터의 에미터가 있는 상기 제1 전도형의 확산영역들을 구비하는 바이폴라 반도체 장치에 있어서, 상기 트랜지스터의 베이스가 있는 상기 제2 전도형의 상기 웰영역은 트랜지스터의 콜렉터가 있는 제1 전도형의 상기 제2 매립층과 접촉하고 트랜지스터의 종방향에서 간격(d)은 상기 웰영역의 상기 에피택셜층을 통하여 상기 트랜지스터의 콜렉터 전극이 있는 상기 확산영역으로 둘러싸여 지고, 제1 전도형의 상기 확산영역의 표면불순물 농도에 의존하여 상기 간격(d)는 소망의 트랜지스터의 CB 접합내압이 조정되고, 제1 전도형의 상기 반도체 기판의 주표면의 소정범위에서 제2 전도형의 상기 제1 매립층을 형성하는 스텝과; 제2 전도형의 상기 제1 매립층에서 제1 전도형의 상기 제2 매립층을 형성하는 스탭과; 제1, 제2 전도형의 상기 제1, 제2 매립층을 포함하는 제1 전도형의 반도체 기판의 모든 표면위에 제2 전도형의 상기 에피택셜층을 형성하는 스텝과; 제1 전도형의 상기 제2 매립층의 표면으로부터 제2 전도형의 상기 웰영역을 형성하는 스텝과; 그런후, 거리(d)의 간격으로 제2 전도형의 상기 웰영역을 둘러싸고 제1 전도형의 상기 제2 매립층에 확장하여 제1 전도형의 상기 확산영역을 형성하는 스텝과; NA(104)는 콜렉터가 되는 상기 제1 전도형 매립층의 불순물농도이고; NA(106)는 콜렉터전극이 되는 상기확산영역의 불순물농도이고; ND(102)는 상기 제2 전도형 에피택셜층의 불순물농도이고; ND(105)는 트랜지스터용 베이스가 되는 상기 제2 전도형 웰영역의 불순물농도인 NA(104) X ND(105) 곱은 NA(106) X ND(102)곱 보다 크게 조정되도록, 제2 전도형의 상기 웰여역에서 제1 전도형의 에미터가 있는 상기 확산영역을 형성하는 스텝을 구비하는 바이폴라 반도체 장치의 제조방법.(7) A bipolar semiconductor device having diffusion regions of the first conductivity type having an emitter of a transistor formed in the well region, wherein the well region of the second conductivity type having a base of the transistor is a collector of a transistor. A gap d in contact with the second buried layer of the first conductivity type, wherein the spacing d in the longitudinal direction of the transistor is surrounded by the diffusion region with the collector electrode of the transistor, through the epitaxial layer of the well region, Depending on the surface impurity concentration of the diffusion region of the conductivity type, the gap d may be adjusted to a CB junction withstand voltage of a desired transistor, and the second conductivity type may be controlled within a predetermined range of the main surface of the semiconductor substrate of the first conductivity type. Forming the first buried layer; A step of forming the second buried layer of the first conductivity type in the first buried layer of the second conductivity type; Forming the epitaxial layer of the second conductivity type on all surfaces of the semiconductor substrate of the first conductivity type including the first and second buried layers of the first and second conductivity type; Forming the well region of a second conductivity type from a surface of the second buried layer of a first conductivity type; Thereafter, surrounding the well region of the second conductivity type at an interval of distance d and extending to the second buried layer of the first conductivity type to form the diffusion region of the first conductivity type; NA 104 is an impurity concentration of the first conductivity type buried layer serving as a collector; NA 106 is an impurity concentration of the diffusion region serving as a collector electrode; ND 102 is an impurity concentration of the second conductivity type epitaxial layer; ND 105 is the second conductivity type so that the NA 104 X ND 105 product, which is the impurity concentration of the second conductivity type well region that is the base for the transistor, is adjusted to be greater than the NA 106 X ND 102 product. And forming the diffusion region with the emitter of the first conductivity type in the well region of the second bipolar semiconductor device. 제6항에 있어서, 트랜지스터의 베이스가 있는 제2 전도형의 상기 웰영역의 일단부터 트랜지스터의 콜렉터가 있는 상기 확산영역의 일단까지의 상기 표면위에 필드산화막을 형성하는 스텝을 더 구성하는 바이폴라 반도체 장치의 제조방법.7. The bipolar semiconductor device according to claim 6, further comprising the step of forming a field oxide film on the surface from one end of the well region of the second conductivity type with the base of the transistor to one end of the diffusion region with the collector of the transistor. Manufacturing method.
KR1019960038940A 1996-06-07 1996-09-09 Bipolar semiconductor device and manufacturing method thereof KR100272636B1 (en)

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JP96-145682 1996-06-07
JP8145682A JPH09330936A (en) 1996-06-07 1996-06-07 Bipolar semiconductor device and its manufacture

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JPH08162473A (en) * 1994-12-09 1996-06-21 Mitsubishi Electric Corp Bipolar semiconductor device and manufacture thereof

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