KR970024262A - Bipolar transistor and method for fabricating - Google Patents

Bipolar transistor and method for fabricating Download PDF

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KR970024262A
KR970024262A KR1019950036680A KR19950036680A KR970024262A KR 970024262 A KR970024262 A KR 970024262A KR 1019950036680 A KR1019950036680 A KR 1019950036680A KR 19950036680 A KR19950036680 A KR 19950036680A KR 970024262 A KR970024262 A KR 970024262A
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region
conductivity type
collector
emitter
base
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KR0163745B1 (en
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강원구
이종호
유종선
유형준
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양승택
한국전자통신연구소
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

본 발명은 바이폴라 트랜지스터 및 그의 제조방법에 관한 것으로서, 제1기둥의 상부에 베이스영역을 형성하고, 이 베이스영역에 에미터 전극으로 부터 불순물을 확산시켜 에미터영역을 형성하므로 베이스영역과 에미터영역의 접촉면이 넓으므로 전류 구동 능력이 크고, 또한, 베이스영역의 기생 저항 및 기생 캐패시턴스가 작다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor and a method for manufacturing the same, wherein a base region is formed on an upper portion of a first pillar, and an emitter region is formed by diffusing impurities from an emitter electrode in the base region, thereby forming a base region and an emitter region. Since the contact surface of is wide, the current driving capability is large, and the parasitic resistance and parasitic capacitance of the base region are small.

또한, 상기 바이폴라 트랜지스터는 저농도 콜렉터영역으로 이용되는 제1기둥 하부의 불순물 농도가 낮고 콜렉터영역의 길이가 길므로 항목 전압 및 어얼리 전압이 높게 된다.In addition, the bipolar transistor has a low impurity concentration in the lower portion of the first pillar used as the low concentration collector region and a long collector region, resulting in high item voltage and early voltage.

따라서, 전류 구동능력이 크고 베이스영역의 기생 저항 및 기생 캐패시턴스가 작으며, 또한, 항복 전압 및 어얼리 전압이 높으므로 고속 디지탈 집적회로 및 아날로그 집적회로에 사용할 수 있어 디지탈 집적회로와 아날로그 집적회로가 혼재된 디지탈 집적회로/아날로그 집적회로를 설계 및 제조할 수 있다.Therefore, since the current driving capability is large, the parasitic resistance and parasitic capacitance of the base region are small, and the breakdown voltage and the early voltage are high, the digital integrated circuit and the analog integrated circuit can be used for high speed digital integrated circuit and analog integrated circuit. Mixed digital integrated circuits / analog integrated circuits can be designed and manufactured.

Description

바이폴라 트랜지스터 및 그의 제조방법(Bipolar transistor and method for fabricating thereof)Bipolar transistor and method for fabricating

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 종래의 수평형 바이폴라 트랜지스터의 단면도,1 is a cross-sectional view of a conventional horizontal bipolar transistor,

제2도는 종래의 수직형 바이폴라 트랜지스터의 단면도,2 is a cross-sectional view of a conventional vertical bipolar transistor,

제3도는 본 발명의 일실시예에 따른 바이폴라 트랜지스터의 단면도,3 is a cross-sectional view of a bipolar transistor according to an embodiment of the present invention;

제4도(A) 내지 (E)는 제3도에 도시된 바이폴라 트랜지스터의 제조 공정도,4A to 4E are manufacturing process diagrams of the bipolar transistor shown in FIG.

제5도는 본 발명의 또 다른 실시예에 따른 바이폴라 트랜지스터의 단면도.5 is a cross-sectional view of a bipolar transistor according to another embodiment of the present invention.

Claims (7)

제1도전형의 반도체 기판과; 상기 반도체 기판 상의 전면에 형성된 매몰 산화층과; 상기 매몰 산화층 상의 소정 부분에 고농도 제1도전형의 콜렉터영역과; 상기 콜렉터영역 상부의 일측 소정 부분에 상부에 상기 제1도전형과 반대 도전형인 제2도전형의 베이스영역이, 이 베이스영역의 상부에 고농도 제1도전형의 에미터영역이, 하부에 제1도전형의 저농도 콜렉터영역 형성된 제1기둥과; 상기 콜렉터영역 상부의 타측 소정 부분에 고농도 제1도전형의 콜렉터 접촉영역이 형성된 제2기둥과; 상기 베이스영역의 측면에 전기적으로 연결되도록 형성된 고농도 제2도전형의 베이스 전극과; 상기 매몰 산화층의 상부에 상기 제1 및 제2기둥과 베이스 전극의 표면이 노출되게 형성된 산화막과, 상기 에미터영역의 상부에 제1도전형이 고농도로 도핑된 다결정실리콘으로 형성된 에미터 전극, 상기 베이스 전극, 에미터 전극 및 콜렉터 접촉영역의 상부에 형성된 베이스 금속전극, 에미터 금속전극 및 콜렉터 금속전극을 포함하는 바이폴라 트랜지스터.A semiconductor substrate of a first conductive type; A buried oxide layer formed on the entire surface of the semiconductor substrate; A collector region of a high concentration first conductivity type in a predetermined portion on the buried oxide layer; The base region of the second conductivity type, which is opposite to the first conductivity type, is formed on one side of the upper portion of the collector region, and the emitter region of the high concentration first conductivity type is disposed on the upper portion, and the first area is disposed on the lower portion. A first pillar having a low concentration collector region of a conductivity type; A second column having a collector contact region of a high concentration first conductivity type on a predetermined portion of the other side of the collector region; A high concentration second conductive base electrode formed to be electrically connected to a side of the base region; An emitter electrode formed of an oxide film formed on the buried oxide layer to expose the surfaces of the first and second pillars and the base electrode, and a polysilicon doped with a high concentration of a first conductivity type on the emitter region; A bipolar transistor comprising a base electrode, an emitter electrode, and a base metal electrode, an emitter metal electrode, and a collector metal electrode formed on the collector contact region. 제1항에 있어서, 상기 매몰 산화층 표면의 상기 제1 및 제2기둥이 형성되지 않은 나머지 부분에 형성된 실리사이드층을 더 포함하는 바이폴라 트랜지스터.The bipolar transistor of claim 1, further comprising a silicide layer formed on the remaining portions of the buried oxide layer, in which the first and second pillars are not formed. 제1도전형의 반도체 기판과; 상기 반도체 기판 상의 전면에 형성된 매몰 산화층과; 상기 매몰 산화층 상의 소정 부분에 고농도 제1도전형의 콜렉터영역과; 상기 콜렉터영역 상부의 일측 소정 부분에 상부에 상기 제1도전형과 반대 도전형인 제2도전형의 베이스영역이, 이 베이스영역의 상부에 고농도 제1도전형의 에미터영역이, 하부에 제1도전형의 저농도 콜렉터영역 형성된 기둥과; 상기 베이스영역의 측면에 전기적으로 연결되도록 형성된 고농도 제2도전형의 베이스 전극과, 상기 매몰 산화층의 상부에 상기 기둥과 베이스 전극의 표면이 노출되게 형성된 절연층과; 상기 에미터영역의 상부에 제1도전형이 고농도로 도핑된 다결정실리콘으로 형성된 에미터 전극; 상기 베이스 전극, 에미터 전극 및 콜렉터영역의 상부에 형성된 베이스 금속전극, 에미터 금속전극, 및 콜렉터 금속전극을 포함하는 바이폴라 트랜지스터.A semiconductor substrate of a first conductive type; A buried oxide layer formed on the entire surface of the semiconductor substrate; A collector region of a high concentration first conductivity type in a predetermined portion on the buried oxide layer; The base region of the second conductivity type, which is opposite to the first conductivity type, is formed on one side of the upper portion of the collector region, and the emitter region of the high concentration first conductivity type is disposed on the upper portion, and the first area is disposed on the lower portion. A pillar having a low concentration collector region of a conductivity type; A high concentration second conductive base electrode formed to be electrically connected to a side surface of the base region, and an insulating layer formed to expose surfaces of the pillars and the base electrode on the buried oxide layer; An emitter electrode formed of polycrystalline silicon doped with a high concentration of a first conductivity type on the emitter region; And a base metal electrode, an emitter metal electrode, and a collector metal electrode formed on the base electrode, the emitter electrode, and the collector region. 제1도전형의 반도체 기판의 내부에 표면에서 소정 깊이에 위치하는 매몰 산화층을 형성하는 공정과; 상기 매몰 산화층 상부의 반도체 기판을 상기 매몰 산화층이 노출되도록 에칭하고 제1도전형의 불순물을 도핑하여 콜렉터영역을 형성하는 공정과; 상기 매몰 산화층과 콜렉터영역의 소정 부분을 제외한 부분의 상부에 산화막을 형성하는 공정과; 상기 산화막의 소정 부분을 2단계의 단차를 갖도록 제거하여 콜렉터영역을 노출시켜 제1 및 제2기둥을 형성하고, 이 제1기둥의 일측과 접촉되는 제2도전형의 베이스 전극을 형성하는 공정과; 상기 제1기둥의 상부에 제2도전형의 베이스영역과 재2기둥에 제1도전형의 콜렉터 접촉영역을 형성하는 공정과; 상기 제1기둥의 상부에 제1도전형의 에미터 전극을 형성하고, 이 에미터 전극에 도핑된 불순물을 상기 제1기둥으로 확산시켜 상기 베이스영역과 접합을 이루는 에미터영역을 형성하는 공정과; 상술한 구조의 전 표면에 산화막을 형성한 후 에미터 전극, 베이스 전극 및 콜렉터 접촉영역을 노출시키고 에미터 금속전극, 베이스 금속전극 및 콜렉터 금속 전극을 형성하는 공정을 구비하는 바이폴라 트랜지스터의 제조방법.Forming a buried oxide layer located at a predetermined depth on a surface of the first conductive semiconductor substrate; Etching the semiconductor substrate on the buried oxide layer to expose the buried oxide layer and doping impurities of a first conductivity type to form a collector region; Forming an oxide film on top of the portion other than the predetermined portion of the buried oxide layer and the collector region; Removing a predetermined portion of the oxide film to have a two-step step to expose a collector region to form first and second pillars, and to form a second conductive base electrode in contact with one side of the first pillar; ; Forming a base region of the second conductivity type on the upper portion of the first pillar and a collector contact region of the first conductivity type on the second pillar; Forming an emitter electrode of a first conductivity type on top of the first pillar and diffusing doped impurities into the first pillar to form an emitter region which is in contact with the base region; ; A method of manufacturing a bipolar transistor comprising forming an emitter electrode, a base electrode, and a collector contact region after forming an oxide film on the entire surface of the above-described structure, and forming an emitter metal electrode, a base metal electrode, and a collector metal electrode. 제4항에 있어서, 상기 콜렉터영역의 소정 부분을 제외한 부분의 표면에 실리사이드층을 형성하는 공정을 더 구비하는 바이폴라 트랜지스터의 제조방법.The method of manufacturing a bipolar transistor according to claim 4, further comprising a step of forming a silicide layer on a surface of a portion excluding a predetermined portion of the collector region. 제4항에 있어서, 상기 콜렉터영역의 노출된 부분에 선택적 에피택셜 방법으로 제1 및 제2기둥을 형성하고, 이 제1 및 제2기둥과 절연층의 상부에 제1도전형이 도핑된 비정질실리콘 또는 다결정실리콘을 증착한 후 절연층의 상부가 노출되도록 연마하여 베이스 전극을 형성하는 바이폴라 트랜지스터의 제조방법.5. The amorphous of claim 4, wherein first and second pillars are formed in an exposed portion of the collector region by a selective epitaxial method, and the first conductive type is doped on top of the first and second pillars and the insulating layer. A method of manufacturing a bipolar transistor after depositing silicon or polycrystalline silicon and polishing the upper portion of the insulating layer to expose the base electrode. 제1도전형의 반도체 기판의 내부에 표면에서 소정 깊이에 위치하는 매몰 산화층을 형성하는 공정과; 상기 매몰 산화층 상부의 반도체 기판을 상기 매몰 산화층이 노출되도록 에칭하고 제1도전형의 불순물을 도핑하여콜렉터영역을 형성하는 공정과; 상기 매몰 산화층과 콜렉터영역의 소정 부분을 제외한 부분의 상부에 산화막을형성하는 공정과; 상기 산화막의 소정 부분을 2단계의 단차를 갖도록 제거하여 콜렉터영역을 노출시켜 기둥을형성하고, 기둥의 일측과 접촉되는 제2도전형의 베이스 전극을 형성하는 공정과; 상기 기둥의 상부에 제2도전형의 베이스영역을 형성하는 공정과; 상기 기둥의 상부에 제1도전형의 에미터 전극을 형성하고, 이 에미터 전극에도핑된 불순물을 상기 기둥으로 확산시켜 상기 베이스영역과 접합을 이루는 에미터영역을 형성하는 공정과; 상술한 구조의 전 표면에 산화막을 형성한 후 에미터 전극, 베이스 전극 및 콜렉터 접촉영역을 노출시키고 에미터 금속전극, 베이스 금속전극 및 콜렉터 금속전극을 형성하는 공정을 구비하는 바이폴라 트랜지스터의 제조방법.Forming a buried oxide layer located at a predetermined depth on a surface of the first conductive semiconductor substrate; Etching the semiconductor substrate over the buried oxide layer to expose the buried oxide layer and doping impurities of a first conductivity type to form a collector region; Forming an oxide film on top of portions other than the predetermined portion of the buried oxide layer and the collector region; Removing a predetermined portion of the oxide film to have a two-step step to expose a collector region to form a pillar, and to form a second conductive base electrode in contact with one side of the pillar; Forming a base region of a second conductivity type on top of the pillar; Forming an emitter electrode of a first conductivity type on top of the pillar, and diffusing doped impurities into the pillar to form an emitter region in contact with the base region; A method of manufacturing a bipolar transistor comprising forming an emitter electrode, a base electrode, and a collector contact region after forming an oxide film on the entire surface of the above structure, and forming an emitter metal electrode, a base metal electrode, and a collector metal electrode. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950036680A 1995-10-23 1995-10-23 A bipolar transistor and method for faricating thereof KR0163745B1 (en)

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KR1019950036680A KR0163745B1 (en) 1995-10-23 1995-10-23 A bipolar transistor and method for faricating thereof

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