KR980006222A - Digital Signal Processing Equipment - Google Patents

Digital Signal Processing Equipment Download PDF

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Publication number
KR980006222A
KR980006222A KR1019960022117A KR19960022117A KR980006222A KR 980006222 A KR980006222 A KR 980006222A KR 1019960022117 A KR1019960022117 A KR 1019960022117A KR 19960022117 A KR19960022117 A KR 19960022117A KR 980006222 A KR980006222 A KR 980006222A
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KR
South Korea
Prior art keywords
identification code
frame
unit
ecc unit
data
Prior art date
Application number
KR1019960022117A
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Korean (ko)
Other versions
KR100192244B1 (en
Inventor
이두희
Original Assignee
구자홍
엘지전자 주식회사
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Application filed by 구자홍, 엘지전자 주식회사 filed Critical 구자홍
Priority to KR1019960022117A priority Critical patent/KR100192244B1/en
Publication of KR980006222A publication Critical patent/KR980006222A/en
Application granted granted Critical
Publication of KR100192244B1 publication Critical patent/KR100192244B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

본 발명은 1싱크블럭에서 순수 데이타뿐만 아니라 식별코드까지 에러정정하도록 하는 디지탈 신호처리장치에 관한 것이다.The present invention relates to a digital signal processing apparatus for performing error correction on not only pure data but also identification codes in one sync block.

본 발명은 입력 디지탈 데이타를 프레임 또는 필드 단위로 ECC하는 프레임 ECC부와, 기록시 상기 프레임 ECC부의 출력 데이타에 식별코드를 삽입하고, 재생시는 기록시에 기록된 식별코드를 검출하여 식별코드의 에러를 정정하며, 에러정정시 식별코드에 다수개의 에러발생시 제어신호에 따라 출력값을 달리하는 처리부와, 상기 식별코드 및 메인 데이타를 에러 정정하는 겸용 ECC부를 구비한다.The present invention inserts an identification code into a frame ECC unit for ECC input digital data on a frame or field basis, and output data of the frame ECC unit at the time of recording, and detects the identification code recorded at the time of recording to reproduce an error of the identification code. And a processing unit for varying an output value according to a control signal when a plurality of errors occur in the identification code upon error correction, and a combined ECC unit for error correction of the identification code and main data.

Description

디지탈 신호처리장치Digital Signal Processing Equipment

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도 (a)는 일반적인 비디오 테이프의 1트랙상의 데이타 포맷, (b)는 일반적인 비디오 테이프의 1싱크 블럭의 데이타 포맷.Figure 1 (a) shows a data format on one track of a typical video tape, and (b) shows a data format of one sync block of a typical video tape.

제2도는 종래의 디지탈 신호처리장치의 구성 블럭도.2 is a block diagram of a conventional digital signal processing apparatus.

Claims (4)

입력 디지탈 데이타를 프레임 또는 필드 단위로 ECC하는 프레임 ECC부와, 기록시 상기 프레임 ECC부의 출력 데이타에 식별코드를 삽입하고, 재생시는 기록시에 기록된 식별코드를 검출하여 식별코드의 에러를 정정하는 식별코드 처리부와, 상기 식별코드 및 메인 데이타를 에러 정정하는 겸용 ECC부를 포함하여 구성됨을 특징으로 하는 디지탈 신호처리장치.A frame ECC unit for ECC input digital data on a frame or field basis, and inserts an identification code into the output data of the frame ECC unit at the time of recording, and detects the identification code recorded at the time of recording to correct errors in the identification code. And an identification code processing unit and a combined ECC unit for error correction of the identification code and the main data. 제1항에 있어서, 상기 겸용 ECC부의 에러 정정 바이트가 식별코드의 바이트 만큼 추가됨을 특징으로 하는 디지탈 신호처리장치.The digital signal processing apparatus according to claim 1, wherein an error correction byte of the combined ECC unit is added as much as a byte of an identification code. 입력 디지탈 데이타를 프레임 또는 필드 단위로 ECC하는 프레임 ECC부와, 기록시 상기 프레임 ECC부의 출력 데이타에 식별코드를 삽입하고, 재생시는 기록시에 기록된 식별코드를 검출하여 식별코드에 다수개의 에러발생시 초기화부의 제어신호에 따라 식별코드를 출력하는 식별코드 처리부와, 상기 식별코드 및 메인 데이타를 에러 정정하는 겸용 ECC부를 포함하여 구성됨을 특징으로 하는 디지탈 신호처리장치.When inserting an identification code into the frame ECC unit for ECC input digital data on a frame or field basis, and the output data of the frame ECC unit during recording, and during reproduction, the identification code recorded at the time of recording is detected and a plurality of errors occur in the identification code. And an identification code processing unit for outputting an identification code according to a control signal of an initialization unit, and a combined ECC unit for error correction of the identification code and main data. 제3항에 있어서, 상기 겸용 ECC부의 처리 바이트는 식별코드 데이타의 추가분 만큼 패리티가 감소됨을 특징으로 하는 디지탈 신호처리장치.4. The digital signal processing apparatus according to claim 3, wherein the processing byte of the combined ECC unit reduces parity by an additional amount of identification code data.
KR1019960022117A 1996-06-18 1996-06-18 Digital signal processor KR100192244B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960022117A KR100192244B1 (en) 1996-06-18 1996-06-18 Digital signal processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960022117A KR100192244B1 (en) 1996-06-18 1996-06-18 Digital signal processor

Publications (2)

Publication Number Publication Date
KR980006222A true KR980006222A (en) 1998-03-30
KR100192244B1 KR100192244B1 (en) 1999-06-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960022117A KR100192244B1 (en) 1996-06-18 1996-06-18 Digital signal processor

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Publication number Publication date
KR100192244B1 (en) 1999-06-15

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