KR980006043A - Device isolation oxide film formation method of semiconductor device - Google Patents

Device isolation oxide film formation method of semiconductor device Download PDF

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KR980006043A
KR980006043A KR1019960023238A KR19960023238A KR980006043A KR 980006043 A KR980006043 A KR 980006043A KR 1019960023238 A KR1019960023238 A KR 1019960023238A KR 19960023238 A KR19960023238 A KR 19960023238A KR 980006043 A KR980006043 A KR 980006043A
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film
oxide film
silicon nitride
device isolation
etching
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KR1019960023238A
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KR100400329B1 (en
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박철수
김대영
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체 소자의 소자분리 산화막 형성방법에 관한 것으로, 실리콘 기판 상부에 패드 산화막, 실리콘 질화막을 차례로 증착한후, 소자분리용 마스크를 사용하여 감광막 패턴을 형성하고 상기 감광막 패턴을 식각장벽으로하여 실리콘 질화막을 식각하되, 일정두께의 질화막을 남긴 후, 상기 실리콘 질화막 측벽에 산화막 스페이서를 형성한 다음, 소자분리 산화막이 성장할 예정된 부위의 하부층을 식각하되, 소자분리 산화막이 실리콘 표면 상부로 과다하게 올라오는 것을 방지하기 위해 실리콘 기판을 일정깊이로 식각한 후 소자분리 산화막을 성장시킴으로써, 소자분리 산화막과 실리콘 표면과의 경계부분에서의 산화막이 실리콘 표면보다 낮게 형성되지 않는 즉, 단차형성이 되지 않게 함으로써 양질의 게이트 산화막을 형성할 수 있고, 또한 실리콘 표면에 스트레스가 완화되어 실리콘 기판의 누설전류도 방지할 수 있다.The present invention relates to a method for forming a device isolation oxide film of a semiconductor device, and sequentially depositing a pad oxide film and a silicon nitride film on a silicon substrate, and then forming a photoresist pattern using a device isolation mask and using the photoresist pattern as an etch barrier. After etching the silicon nitride film, leaving a nitride film of a predetermined thickness, forming an oxide spacer on the silicon nitride sidewall, and then etching the lower layer of the region where the device isolation oxide is to be grown, the device isolation oxide is excessively raised above the silicon surface In order to prevent the silicon substrate from being etched to a certain depth, the device isolation oxide film is grown, and the oxide film at the boundary between the device isolation oxide film and the silicon surface is not formed lower than the silicon surface, that is, the step is not formed. Can form a high quality gate oxide film, Stress on the silicon surface is relieved to prevent leakage of the silicon substrate.

Description

반도체 소자의 소자분리 산화막 형성방법Device isolation oxide film formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본발명의 방법에 따른 반도체 소자의 소자분리 산화막 제조공정 단계를 도시한 단면도이다.1 is a cross-sectional view showing a device isolation oxide film manufacturing process step of a semiconductor device according to the present invention.

제8도는 본발명의 방법에 따른 반도체 소자의 소자분리 산화막 제조공정 단계를 도시한 단면도이다.8 is a cross-sectional view illustrating a process of fabricating a device isolation oxide film of a semiconductor device according to the present invention.

Claims (9)

반도체 소자의 소자분리 산화막 형성방법에 있어서, 실리콘 기판 상부에 패드 산화막을 형성하고, 그 상부에 실리콘 질화막을 형성하는 공정과, 전체구조 상부에 감광막을 코팅하는 단계와, 소자분리용 마스크를 사용하여 노광 및 현상하여 감광막으로 소자분리 패턴을 하는 형성하는 공정과, 상기 감광막 패턴을 식각 장벽으로하여 상기 실리콘 질화막을 식각하되 소정두께 잔류하도록 식각하는 공정과, 감광막을 제거하는 공정과, 전체구조 상부에 산화막을 일정 두께로 증착한 다음 상기 산화막을 전면식각하여 상기 실리콘 질화막 측벽에 산화막 스페이서를 형성하는 공정과, 상기 산화막 스페이서를 식각장벽으로하여 하부의 실리콘 질화막을 실리콘 기판의 표면이 노출되기 까지 식각하는 공정과, 소자분리 산화막을 성장시키는 공정으로 구성되는 것을 특징으로하는 반도체 소자의 소자분리 산화막 형성방법.A method of forming a device isolation oxide film of a semiconductor device, comprising: forming a pad oxide film on a silicon substrate, forming a silicon nitride film on the silicon substrate, coating a photoresist film on the entire structure, and using a device separation mask Forming a device isolation pattern with a photosensitive film by exposure and development, etching the silicon nitride film using the photosensitive film pattern as an etch barrier, and etching such that the silicon nitride film remains at a predetermined thickness, removing the photosensitive film, and Depositing an oxide film to a predetermined thickness and then etching the oxide film to form an oxide spacer on the sidewall of the silicon nitride layer; and etching the lower silicon nitride layer until the surface of the silicon substrate is exposed using the oxide spacer as an etch barrier. Process and growing a device isolation oxide film The device isolation oxide film formation method of a semiconductor device, characterized in that. 제1항에 있어서, 상기 패드 산화막은 산소와 반응되어 산화되는 것을 특징으로하는 반도체 소자의 소자분리 산화막 형성방법.The method of claim 1, wherein the pad oxide film is reacted with oxygen and oxidized. 제1항에 있어서, 상기 스페이서는 질화막으로 형성되는 것을 특징으로하는 반도체 소자의 소자분리 산화막 형성방법.The method of claim 1, wherein the spacer is formed of a nitride film. 제1항에 있어서, 상기 스페이서 형성후 실리콘 질화막 식각시 잔류 실리콘 질화막만 식각하고 패드 산화막을 식각하지 않은 상태에서 소자분리 산화막을 성장시키는 것을 특징으로하는 반도체 소자의 소자분리 산화막 형성방법.The method of claim 1, wherein after the spacers are formed, only the remaining silicon nitride layer is etched and the device isolation oxide layer is grown without etching the pad oxide layer. 반도체 소자의 소자분리 산화막 형성방법에 있어서, 실리콘 기판 상부에 패드 산화막을 형성하고, 그 상부에 실리콘 질화막을 형성하는 공정과, 전체구조 상부에 감광막을 코팅하는 단계와, 소자분리용 마스크를 사용하여 노광 및 현상하여 감광막으로 소자분리 패턴을 형성하는 공정과, 상기 감광막 패턴을 식각 장벽으로하여 상기 실리콘질화막을 식각하되 소정두께 잔류하도록 식각하는 공정과, 감광막을 제거하는 공정과, 전체구조 상부에 산화막을 일정 두께로 증착한 다음 상기 산화막을 전면식각하여 상기 실리콘 질화막 측벽에 산화막 스페이서를 형성하는 공정과, 전면식각으로 하부의 실리콘 기판 표면이 노출되도록 실리콘 질화막과 패드 산화막을 차레로 식각하는 공정과, 상기 노출된 실리콘 기판 표면을 일정두께로 식각하는 공정과, 소자분리 산화막을 성장시키는 공정으로 구성되는 것을 특징으로하는 반도체 소자의 소자분리 산화막 형성방법.A method of forming a device isolation oxide film of a semiconductor device, comprising: forming a pad oxide film on a silicon substrate, forming a silicon nitride film on the silicon substrate, coating a photoresist film on the entire structure, and using a device separation mask Exposing and developing the device isolation pattern to a photoresist film; etching the silicon nitride film using the photoresist pattern as an etch barrier, and etching the silicon nitride film to a predetermined thickness; removing the photoresist film; and removing an oxide film over the entire structure. Forming a oxide spacer on the silicon nitride film sidewalls by depositing the oxide layer to a predetermined thickness, and etching the silicon nitride film and the pad oxide film in order to expose the lower surface of the silicon substrate through the front etching; Etching the exposed silicon substrate surface to a predetermined thickness, and An isolation oxide film formation method of a semiconductor device according to claim consisting of the step of growing an isolation oxide film. 제5항에 있어서, 상기 패드 산화막은 산소와 반응되어 산화되는 것을 특징으로하는 반도체 소자의 소자분리 산화막 형성방법.The method of claim 5, wherein the pad oxide film is reacted with oxygen and oxidized. 제5항에 있어서, 상기 패드 산화막 형성시 패드 산화막을 따로 산화시키지 않고, 실리콘 질화막 증착시 산소 분위기를 유지시킨 후 질화막을 증착하는 공정에서 산호 분위기가 유지시 패드 산화막이 형성되도록 하는 것을 특징으로하는 반도체 소자의 소자분리 산화막 형성방법.The method of claim 5, wherein the pad oxide layer is not oxidized separately when the pad oxide layer is formed, and the pad oxide layer is formed when the coral atmosphere is maintained in the process of maintaining the oxygen atmosphere during the deposition of the silicon nitride layer and then depositing the nitride layer. A device isolation oxide film formation method of a semiconductor device. 제5항에 있어서, 상기 스페이서는 질화막으로 형성되는 것을 특징으로하는 반도체 소자의 소자분리 산화막 형성방법.The method of claim 5, wherein the spacer is formed of a nitride film. 제5항에 있어서, 상기 스페이서 형성후 실리콘 질화막 식각시 잔류 실리콘 질화막만 식각하고 패드 산화막을 식각하지 않은 상태에서 소자분리 산화막을 성장시키는 것을 특징으로하는 반도체 소자의 소자분리 산화막 형성방법.The method of claim 5, wherein after the spacer is formed, the device isolation oxide layer is grown while only the remaining silicon nitride layer is etched and the pad oxide layer is not etched when the silicon nitride layer is etched. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960023238A 1996-06-24 1996-06-24 Method for forming isolation oxide layer of semiconductor device KR100400329B1 (en)

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KR950021381A (en) * 1993-12-29 1995-07-26 김주용 Field oxide film formation method of a semiconductor device
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