KR980006038A - Method of forming device isolation region in semiconductor device - Google Patents

Method of forming device isolation region in semiconductor device Download PDF

Info

Publication number
KR980006038A
KR980006038A KR1019960021857A KR19960021857A KR980006038A KR 980006038 A KR980006038 A KR 980006038A KR 1019960021857 A KR1019960021857 A KR 1019960021857A KR 19960021857 A KR19960021857 A KR 19960021857A KR 980006038 A KR980006038 A KR 980006038A
Authority
KR
South Korea
Prior art keywords
oxide layer
layer
forming
silicon substrate
spacer
Prior art date
Application number
KR1019960021857A
Other languages
Korean (ko)
Other versions
KR0183887B1 (en
Inventor
한용운
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960021857A priority Critical patent/KR0183887B1/en
Publication of KR980006038A publication Critical patent/KR980006038A/en
Application granted granted Critical
Publication of KR0183887B1 publication Critical patent/KR0183887B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 실리콘 기판에 트렌치를 형성하여서 소자 분리막을 형성하는 반도체 장치의 소자 분리 영역 형성 방법에 관하여 기재하고 있다. 이는, 실리콘 기판상에 제1산화물층, 제1질화물층, 제1고온산화물층을 순차적으로 적층 형성시킴으로서 다수 절연층을 형성하는 단계와, 김광층을 식각 마스크로하여서 상기 다수 절연층의 일부를 순차적으로 식각하여 패터닝시키는 단계와, 상기 다수 절연층의 패턴을 통하여 노출된 상기 실리콘 기판의 일부를 열산화시켜서 제2산화물층을 형성하는 단계와, 상기 제2산화물층이 형성된 실리콘 기판의 전면에 실리콘 질화물을 소정 두께로 증착시켜서 제2질화물층을 형성하는 단계와, 상기 제2질화물층을 건식식각 공정에 의하여 식각시킴으로서 제1스페이서를 형성하는 단계와, 상기 제1스페이서를 구비한 실리콘 기판의 전면에 제2 고온 산화물층을 형성하는 단계와, 상기 제2 고온산화물층을 건식 식각공정에 의하여 식각시킴으로서 제2 스페이서를 형성하는 단계와, 상기 제2스페이서의 패턴을 통하여 노출된 상기 실리콘 기판을 열산화시킴으로서 제3산화물층을 형성하는 단계와, 상기 제2스페이서를 식각 마스크로하여 상기 실리콘 기판에 트렌치를 형성하는 단계와, 상기 트렌치를 구비한 실리콘 기판의 전면에 절연 물질을 적층시켜서 소자 분리막을 구비한 절연층을 형성시키는 단계, 평탄화 공정 및 식각 공정에 의하여 실리콘 기판의 활성 영역 및 소자 분리막의 표면을 노출시키는 단계로 이루어진다. 따라서, 본 발명에 따르면, 소자 분리막의 에지 영역에 작용하는 스트레스의 영향을 저감시킬 수 있을뿐만 아니라 정렬 마진을 최대화시킬 수 있으며 그 결과 누설 전류를 제거할 수 있다.The present invention describes a method of forming an isolation region in a semiconductor device in which a trench is formed in a silicon substrate to form an isolation layer. This is performed by forming a plurality of insulating layers by sequentially stacking a first oxide layer, a first nitride layer, and a first high temperature oxide layer on a silicon substrate. Etching and patterning sequentially, thermally oxidizing a portion of the silicon substrate exposed through the pattern of the plurality of insulating layers to form a second oxide layer, and a front surface of the silicon substrate on which the second oxide layer is formed. Forming a second nitride layer by depositing silicon nitride to a predetermined thickness; forming a first spacer by etching the second nitride layer by a dry etching process; and forming a second spacer layer of the silicon substrate including the first spacer. Forming a second high temperature oxide layer on the entire surface, and etching the second high temperature oxide layer by a dry etching process to form a second spacer. Forming a third oxide layer by thermally oxidizing the silicon substrate exposed through the pattern of the second spacer, and forming a trench in the silicon substrate using the second spacer as an etch mask. And forming an insulating layer including an isolation layer by stacking an insulating material on the entire surface of the silicon substrate including the trench, exposing an active region of the silicon substrate and a surface of the isolation layer by a planarization process and an etching process. Is made of. Therefore, according to the present invention, not only the influence of stress acting on the edge region of the device isolation layer can be reduced, but also the alignment margin can be maximized, and as a result, leakage current can be eliminated.

Description

반도체 장치의 소자분리 영역 형성방법Device isolation region formation method of a semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제10도는 본 발명의 실시예에 따라서 소자 분리막을 형성하는 방법을 순차적으로 도시한 단면도.10 is a cross-sectional view sequentially illustrating a method of forming an isolation layer in accordance with an embodiment of the present invention.

제16도는 본 발명의 실시예에 따라서 소자 분리막을 형성하는 방법을 순차적으로 도시한 단면도.FIG. 16 is a cross-sectional view sequentially illustrating a method of forming an isolation layer in accordance with an embodiment of the present invention. FIG.

Claims (10)

실리콘 기판상에 제1산화물층, 제1질화물층, 제1고온산화물층을 순차적으로 적층 형성시킴으로서 다수 절연층을 형성하는 단계와, 감광층을 식각 마스크로하여서 상기 다수 절연층의 일부를 순차적으로 식각하여 패터닝시키는 단계와, 상기 다수 절연층의 패턴을 통하여 노출된 상기 실리콘 기판의 일부를 열산화시켜서 제2산화물층을 형성하는 단계와, 상기 제2산화물층이 형성된 실리콘 기판의 전면에 실리콘 질화물을 소정 두께로 증착시켜서 제2질화물층을 형성하는 단계와, 상기 제2질화물층을 건식식각 공정에 의하여 식각시킴으로서 제1스페이서를 형성하는 단계와, 상기 제1스페이서를 구비한 실리콘 기판의 전면에 제2 고온 산화물층을 형성하는 단계와, 상기 제2 고온산화물층을 건식 식각공정에 의하여 식각시킴으로서 제2 스페이서를 형성하는 단계와, 상기 제2스페이서의 패턴을 통하여 노출된 상기 실리콘 기판을 열산화시킴으로서 제3산화물층을 형성하는 단계와, 상기 제2스페이서를 식각 마스크로하여 상기 실리콘 기판에 트렌치를 형성하는 단계와, 상기 트렌치를 구비한 실리콘 기판의 전면에 절연물질을 적층시켜서 소자 분리막을 구비한 절연층을 형성하는 단계와, 평탄화 공정 및 식각공정에 의하여 실리콘기판의 활성영역 및 소자 분리막의 표면을 노출시키는 단계로 이루어진 것을 특징으로 하는 반도체 장치의 소자분리 영역 형성 방법.Forming a plurality of insulating layers by sequentially stacking a first oxide layer, a first nitride layer, and a first high temperature oxide layer on a silicon substrate, and using a photosensitive layer as an etch mask, a part of the plurality of insulating layers sequentially Etching and patterning, thermally oxidizing a portion of the silicon substrate exposed through the pattern of the plurality of insulating layers to form a second oxide layer, and silicon nitride on the entire surface of the silicon substrate on which the second oxide layer is formed Forming a second nitride layer by depositing to a predetermined thickness, forming a first spacer by etching the second nitride layer by a dry etching process, and forming a first spacer on the entire surface of the silicon substrate including the first spacer. Forming a second high temperature oxide layer, and etching the second high temperature oxide layer by a dry etching process to form a second spacer. Forming a third oxide layer by thermally oxidizing the silicon substrate exposed through the pattern of the second spacer; forming a trench in the silicon substrate using the second spacer as an etch mask; Stacking an insulating material on the entire surface of the silicon substrate including the trench to form an insulating layer including an isolation layer, and exposing an active region of the silicon substrate and a surface of the isolation layer by a planarization process and an etching process A device isolation region forming method of a semiconductor device, characterized in that consisting of. 제1항에 있어서, 상기 제2 질화물층의 적층 두께는 250Å 내지300Å으로 유지되는 것을 특징으로 하는 반도체 장치의 소자 분리 영역 형성 방법.The method of claim 1, wherein the thickness of the second nitride layer is maintained at about 250 GPa to about 300 GPa. 제2항에 있어서, 상기 제2 질화물층은 상기 제1 고온 산화물층상에 소정 두께로 증착될 뿐만 아니라 상기 다수 절연층 패턴의 측벽에 소정 두께로 증착되는 것을 특징으로 하는 반도체 장치의 소자 분리 영역 형성 방법.The device isolation region of claim 2, wherein the second nitride layer is not only deposited to a predetermined thickness on the first high temperature oxide layer but also to a sidewall of the plurality of insulating layer patterns. Way. 제3항에 있어서, 상기 제1 스페이서는 상기 다수 절연층 패턴의 측벽에 잔존하는 상기 제2 질화물층으로 이루어져 있는 것을 특징으로 하는 반도체 장치의 소자 분리 영역 형성 방법.The method of claim 3, wherein the first spacer comprises the second nitride layer remaining on sidewalls of the plurality of insulating layer patterns. 제4항에 있어서, 상기 제2 고온 산화물층의 적층 두께는 300Å 내지 1000Å으로 유지되는 것을 특징으로 하는 반도체 장치의 소자 분리 영역 형성 방법.5. The method of claim 4, wherein the stack thickness of the second high temperature oxide layer is maintained at 300 to 1000 mW. 제5항에 있어서, 상기 제2 고온 산화물층은 상기 제1 고온 산화물층상에 소정 두께로 증착될 뿐만 아니라 상기 제1 스페이서의 측벽에 소정 두께로 증착되는 것을 특징으로 하는 반도체 장치의 소자 분리 영역 형성 방법.The device isolation region of claim 5, wherein the second high temperature oxide layer is deposited not only to a predetermined thickness on the first high temperature oxide layer but also to a sidewall of the first spacer. Way. 제6항에 있어서, 상기 제2 스페이서는 제1 스페이서의 측벽에 잔존하는 상기 제2 고온 산화물층의 일부로 구성되는 것을 특징을 하는 반도체 장치의 소자 분리 영역 형성 방법.The method of claim 6, wherein the second spacer is formed of a portion of the second high temperature oxide layer remaining on sidewalls of the first spacer. 제7항에 있어서, 상기 제3 산화물층의 적층 두께는 500Å 내지 2000Å으로 유지되는 것을 특징으로 하는 반도체 장치의 소자 분리 영역 형성 방법.8. The method of claim 7, wherein the thickness of the third oxide layer is maintained at about 500 GPa to 2000 GPa. 제1항에 있어서, 상기 제1 산화물층은 습식식각 공정에 의하여 제거되는 것을 특징으로 하는 반도체 장치의 소자 분리 영역 형성 방법.The method of claim 1, wherein the first oxide layer is removed by a wet etching process. 제9항에 있어서, 상기 제1 산화물층은 오버 에칭되어서 언더 컷 형상의 단면을 제공하는 것을 특징으로 하는 반도체 장치의 소자분리영역 형성 방법.10. The method of claim 9, wherein the first oxide layer is over-etched to provide an undercut cross section. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960021857A 1996-06-17 1996-06-17 Element isolated range of semiconductor device KR0183887B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960021857A KR0183887B1 (en) 1996-06-17 1996-06-17 Element isolated range of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960021857A KR0183887B1 (en) 1996-06-17 1996-06-17 Element isolated range of semiconductor device

Publications (2)

Publication Number Publication Date
KR980006038A true KR980006038A (en) 1998-03-30
KR0183887B1 KR0183887B1 (en) 1999-04-15

Family

ID=19462164

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960021857A KR0183887B1 (en) 1996-06-17 1996-06-17 Element isolated range of semiconductor device

Country Status (1)

Country Link
KR (1) KR0183887B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090060060A (en) * 2007-12-07 2009-06-11 박승찬 Accessory a pattern formation construction and the rim of a pair of spectacles accessory sticking method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090060060A (en) * 2007-12-07 2009-06-11 박승찬 Accessory a pattern formation construction and the rim of a pair of spectacles accessory sticking method

Also Published As

Publication number Publication date
KR0183887B1 (en) 1999-04-15

Similar Documents

Publication Publication Date Title
KR960002851A (en) Capacitor Manufacturing Method of Semiconductor Device
KR940012650A (en) Contact manufacturing method of semiconductor device
KR970072380A (en) Semiconductor device and manufacturing method thereof
KR980006038A (en) Method of forming device isolation region in semiconductor device
KR20000042870A (en) Forming method of trench of semiconductor device
KR100528797B1 (en) Method of forming an isolation film in a semiconductor device
KR970023978A (en) Method for manufacturing planar device isolation film of semiconductor device
KR100364124B1 (en) Method for manufacturing isolation layer in semiconductor device
KR100505596B1 (en) Method for forming contacts of a semiconductor device
KR970003780A (en) Method of manufacturing device isolation oxide film of semiconductor device
KR960008563B1 (en) Fine contact hall forming method of semiconductor using double spacer
KR970013203A (en) Method of forming device isolation film in semiconductor device
KR100195192B1 (en) Pad poly forming method of semiconductor device
KR970053380A (en) Device Separation Method of Semiconductor Device
KR940003222B1 (en) Prevention method for isolation birds beak by using mlr-structure
KR100400763B1 (en) Method for manufacturing capacitor of semiconductor device
KR970053437A (en) Device isolation film formation method using trench
KR100258857B1 (en) Manufacturing method for isolation structure of semiconductor device
KR970053372A (en) Device Separation Method of Semiconductor Device
KR970018363A (en) Locus and trench combination device isolation method of semiconductor device
KR20000019879A (en) Method for forming gate
KR960002743A (en) Semiconductor device separated by trench and field insulating film and manufacturing method thereof
KR980006316A (en) Manufacturing method of semiconductor device
KR19990032753A (en) Semiconductor Device Separation Method
KR960043103A (en) Device isolation insulating film formation method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20061128

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee