KR980005803A - Thin Film Formation Method of Semiconductor Device - Google Patents

Thin Film Formation Method of Semiconductor Device Download PDF

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Publication number
KR980005803A
KR980005803A KR1019960022601A KR19960022601A KR980005803A KR 980005803 A KR980005803 A KR 980005803A KR 1019960022601 A KR1019960022601 A KR 1019960022601A KR 19960022601 A KR19960022601 A KR 19960022601A KR 980005803 A KR980005803 A KR 980005803A
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South Korea
Prior art keywords
insulating film
film
gas
forming
semiconductor device
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KR1019960022601A
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Korean (ko)
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KR100213204B1 (en
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김창규
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김광호
삼성전자 주식회사
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Publication of KR980005803A publication Critical patent/KR980005803A/en
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Publication of KR100213204B1 publication Critical patent/KR100213204B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체장치의 박막 형성방법에 과해 개시한다. 본 발명에 의한 박막 형성방법은 하지막 의존성을 갖는 절연막을 형성하기전에 상기 하지막(이하, 제1절연막 이라 한다)과 상기 제1절연막 상에 형성된 패턴의 전면에 상기 절연막의 상기 제1절연막에 대한 의존성을 줄이기 위해 일정두께의 제2절연막을 형성하는 것을 특징으로 한다. 따라서 본 발명에 의한 반도체장치의 박막 형성방법은 하지막에 따라 의존성이 간한 절연막을 형성하는데 있어서, 절연막의 형성속도를 전체적으로 고르고 종래 기술에 의한 것보다 빨리 형성할 수 있으므로 종래 기술에 의한 겻보다 균일하고 평탄도가 우수한 절연막을 제공할 수 있다.The present invention relates to a method for forming a thin film of a semiconductor device. In the thin film forming method according to the present invention, the base film (hereinafter referred to as a first insulating film) and the pattern formed on the first insulating film are formed on the first insulating film of the insulating film before forming the insulating film having the underlying film dependency. In order to reduce the dependence on the second insulating film having a predetermined thickness. Therefore, in the method for forming a thin film of a semiconductor device according to the present invention, in forming an insulating film having a small dependence on the underlying film, the insulating film is uniformly formed and can be formed faster than that according to the prior art. And an excellent insulating film can be provided.

Description

반도체장치의 박막 형성방법Thin Film Formation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 의한 반도체장치의 박막 형성방법을 단계별로 나타낸 도면들이다.3 is a diagram showing step by step a method of forming a thin film of a semiconductor device according to the present invention.

Claims (12)

하지막 의존성을 갖는 절연막을 형성하기 전에 상기 하지막(이하, 제1절연막이라 한다)과 상기 제1절연막 상에 형성된 패턴의 전면에 상기 절연막의 상기 제1절연막에 대한 의존성을 줄이기 위해 일정두께의 제2절연막을 형성하는 것을 특징으로 하는 반도체장치의 박막 형성방법.Before forming the insulating film having the underlying film dependency, the base film (hereinafter referred to as a first insulating film) and a predetermined thickness in order to reduce the dependency on the first insulating film of the insulating film on the entire surface of the pattern formed on the first insulating film. A method of forming a thin film of a semiconductor device, comprising forming a second insulating film. 제1항에 있어서, 상기 절연막은 오존( O3)과 테오스(TEOS)에 의한 USG막, 오존( O3)과 HMDS(Hexamethyldisilazane)를 혼합한 가스에 의한 USG막 또는 오존과 실리콘(Si)을 포함하는 유기소오스와 반응에 의해 형성되는 산화막으로 이루어진 일군중 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체장치의 박막 형성방법.The method of claim 1, wherein the insulating film is a USG film formed by ozone (O 3 ) and Teos (TEOS), a USG film formed by a mixture of ozone (O 3 ) and HMDS (Hexamethyldisilazane), or ozone and silicon (Si). The thin film forming method of a semiconductor device, characterized in that formed in any one selected from the group consisting of an oxide film formed by reaction with an organic source comprising a. 제1항에 있어서, 상기 제2절연막은 상기 제1절연막을 구성하는 물질과 질소(N2)가 결합된 질화물막으로 형성하는 것을 특징으로 하는 반도체장치의 박막 형성방법.The method of claim 1, wherein the second insulating layer is formed of a nitride film in which a material constituting the first insulating layer and nitrogen (N 2 ) are bonded to each other. 제3항에 있어서 상기 질화물막은 나이트라이데이션(Nitridation) 공정으로 형성하는 것을 특징으로 하는 박막 형성방법.The method of claim 3, wherein the nitride film is formed by a nitridation process. 제3항에 있어서, 사익 나이트라이데이션(Nitridation) 공정에서는 저압기상화학증착(LPCVD) 방법으로 일정온도 조건하에서 특정 가스를 플로우(flow) 시키는 것을 특징으로 하는 반도체장치의 박막 형성방법.4. The method of claim 3, wherein in a nitridation process, a specific gas is flowed under a constant temperature condition by low pressure vapor deposition (LPCVD). 제4항에 있어서, 상기 특정가스의 플로우는 500℃이상의 온도에서 플로우시키는 데 바람직하게는 780℃에서 플로우 시키는 것을 특징으로 하는 반도체장치의 박막 형성방법.The method of claim 4, wherein the specific gas flows at a temperature of 500 ° C. or higher, preferably at 780 ° C. 6. 제4항 또는 제5항에 있어서, 상기 특정가스로는 단일 성분가스 또는 혼합가스를 선택적으로 사용하는 것을 특징으로 하는 반도체장치의 박막 형성방법.6. The method of forming a thin film of a semiconductor device according to claim 4 or 5, wherein a single component gas or a mixed gas is selectively used as the specific gas. 제6항에 있어서, 상기 단일성분가스로는 암모니아(NH3) 가스를 사용하는 것을 특징으로 하는 반도체장치의 박막 형성방법.The method of claim 6, wherein ammonia (NH 3 ) gas is used as the single component gas. 제6항에 있어서, 상기 단일성분가스로는 암모니아(NH3) 가스와 질소(N2)가스를 사용하는 것을 특징으로 하는 반도체장치의 박막 형성방법.The method of claim 6, wherein the single component gas comprises ammonia (NH 3 ) gas and nitrogen (N 2 ) gas. 제1항에 있어서, 사익 절연막은 상기 패턴의 단차에따라 그 ㅎ여성방법을 다르게하는 것을 특징으로 하는 반도체장치으 ㅣ박막 형성방법.2. The method according to claim 1, wherein the saik insulating film is different in its female method according to the step difference of the pattern. 제9항에 있어서, 상기 패턴의 단차가 클 경우 상기 절연막을 두껍게 형성한 다음 상기 패턴이 노출되지 않는 범위내에서 상기 절연막의 전면을 에치 백하는 것을 특징으로 하는 반도체장치의 박막 형성방법.10. The method of claim 9, wherein if the step difference is large, the insulating film is formed thick and then the entire surface of the insulating film is etched back within the range where the pattern is not exposed. 제9항에 있어서, 상기 패턴의 단차가 작을 경우 상기 절연막을 얇게 형성하고 에치 백 공정을 생략하는 것을 특징으로 하는 반도체장치의 박막 형성방법.10. The method of claim 9, wherein when the pattern is small, the insulating film is formed thin and the etch back process is omitted. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960022601A 1996-06-20 1996-06-20 Method of forming thin film of semiconductor device KR100213204B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100876532B1 (en) * 2004-08-27 2008-12-31 동부일렉트로닉스 주식회사 Manufacturing Method of Semiconductor Device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100876532B1 (en) * 2004-08-27 2008-12-31 동부일렉트로닉스 주식회사 Manufacturing Method of Semiconductor Device

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