KR980005733A - Method for manufacturing semiconductor device by chemical mechanical flinging - Google Patents

Method for manufacturing semiconductor device by chemical mechanical flinging Download PDF

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Publication number
KR980005733A
KR980005733A KR1019960023690A KR19960023690A KR980005733A KR 980005733 A KR980005733 A KR 980005733A KR 1019960023690 A KR1019960023690 A KR 1019960023690A KR 19960023690 A KR19960023690 A KR 19960023690A KR 980005733 A KR980005733 A KR 980005733A
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KR
South Korea
Prior art keywords
sog
chemical mechanical
semiconductor device
mechanical polishing
manufacturing
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KR1019960023690A
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Korean (ko)
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KR100207476B1 (en
Inventor
최지현
황병근
이해정
구주선
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김광호
삼성전자 주식회사
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Priority to KR1019960023690A priority Critical patent/KR100207476B1/en
Publication of KR980005733A publication Critical patent/KR980005733A/en
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Publication of KR100207476B1 publication Critical patent/KR100207476B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

Abstract

화학기계적 폴리싱에 의한 에치백 평탄화공정을 이용하는 반도체 장치의 제조방법을 제공하는 것이다. 반도체 기판상에 도전물질을 증착한 다음 패터닝하여 도전층 패턴을 형성하는 단계; 도전층 패턴이 형성된 상기 결과물상에 제1절연막을 형성하는 단계; 상기 제1절연막상에 SOG층을 형성하고 열처리하는 단계; 상기 SOG층상에 제2절연막을 형성하는 단계; 상기 결과물을 화학기계적 폴리싱 공정을 이용하여 에치백 평탄화하는 것을 특징으로하는 반도체 장치의 제조방법을 제공하는 것이다. 상기 화학기계적 폴리싱 공정의 평탄화는 상기 도전층 패턴 위부분의 SOG까지 제거하여 비어 콘택 부위에 SOG가 남지 않게 하는 것이 바람직하다. 따라서, 본 발명에 의한 화학기계적 폴리싱에 의한 에치백공정으로 종래 화학기계적 폴리싱 공정의 평탄화 방법에 따라 층간절연층을 평탄화시키는 경우 발생되는 디싱(dishing)현상을 방지할 수 있는 반도체 장치의 제조방법을 얻게된다.A semiconductor device manufacturing method using an etch back planarization process by chemical mechanical polishing is provided. Depositing a conductive material on the semiconductor substrate and then patterning to form a conductive layer pattern; Forming a first insulating film on the resultant formed with the conductive layer pattern; Forming and thermally treating an SOG layer on the first insulating layer; Forming a second insulating film on the SOG layer; It is to provide a method for manufacturing a semiconductor device characterized in that the etch back planarization using the resultant chemical mechanical polishing process. The planarization of the chemical mechanical polishing process may remove SOG above the conductive layer pattern so that SOG does not remain in the via contact region. Accordingly, a method of manufacturing a semiconductor device capable of preventing dishing from occurring when the interlayer insulating layer is planarized according to the planarization method of the conventional chemical mechanical polishing process by the etch back process by chemical mechanical polishing according to the present invention. Get

Description

화학기계적 폴리싱에 의한 반도체 장치의 제조방법Method for manufacturing semiconductor device by chemical mechanical polishing

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명의 화학기계적 폴리싱 평탄화방법을 설명하기 위한 단면도이다.4 is a cross-sectional view for explaining the chemical mechanical polishing planarization method of the present invention.

Claims (8)

반도체 기판상에 도전물질을 증착한 다음 패터닝하여 도전층 패턴을 형성하는 단계; 도전층 패턴이 형성된 상기 결과물상에 제1절연막을 형성하는 단계; 상기 제1절연막상에 SOG층을 형성하고 열처리하는 단계; 상기 SOG층상에 제2절연막을 형성하는 단계; 상기 결과물을 화학기계적 폴리싱 공정을 이용하여 에치백 평탄화하는 것을 특징으로하는 반도체 장치의 제조방법.Depositing a conductive material on the semiconductor substrate and then patterning to form a conductive layer pattern; Forming a first insulating film on the resultant formed with the conductive layer pattern; Forming and thermally treating an SOG layer on the first insulating layer; Forming a second insulating film on the SOG layer; And etch-back planarization of the resultant using a chemical mechanical polishing process. 제1항에 있어서, 상기 제1절연막, 상기 SOG층, 상기 제2절연막은 화학기계적 폴리싱 공정의 제거속도 비가 제1절연막 ≤제2절연막 SOG가 되도록 절연물질을 선택하는 것을 특징으로하는 반도체장치의 제조방법.The semiconductor device of claim 1, wherein the first insulating layer, the SOG layer, and the second insulating layer select an insulating material such that a removal rate ratio of a chemical mechanical polishing process becomes a first insulating film ≤ a second insulating film SOG. Manufacturing method. 제1항에 있어서, 상기 화학기계적 폴리싱 공정의 평탄화는 상기 도전층 패턴 위 부분의 SOG까지 제거하여 비어 콘택 부위에 SOG가 남지 않게 하는 것을 특징으로하는 반도체 장치의 제조방법.The method of claim 1, wherein the planarization of the chemical mechanical polishing process removes SOG above the conductive layer pattern so that no SOG remains in the via contact region. 제1항에 있어서, 상기 SOG의 열처리는 300℃∼450℃에서 하는 것을 특징으로하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment of the SOG is performed at 300 ° C to 450 ° C. 제1항에 있어서, 상기 SOG층의 두께는 도전층 두께의1/2 이하가 되는 것을 특징으로하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the SOG layer is 1/2 or less of the thickness of the conductive layer. 제1항에 있어서, 상기 제1절연막과 제2절연막은 SiO2, SiN, SiON, SiOF, SiC 및 BN중 어느하나를 선택하여 사용하는 것을 특징으로하는 반도체 장치의 제조방법.The method of claim 1, wherein the first insulating film and the second insulating film are selected from any one of SiO 2 , SiN, SiON, SiOF, SiC, and BN. 제1항에 있어서, 상기 SOG물질은 화학기계적 폴리싱공정에서 실리카 슬러리를 사용할 경우 무기계 SOG를, 시리어(ceria) 슬러리를 사용할 경우 무기계, 유기계 SOG 및 폴리머 등을 사용하는 것을 특징으로하는 반도체 장치의 제조방법.The semiconductor device of claim 1, wherein the SOG material is an inorganic SOG when using a silica slurry in a chemical mechanical polishing process, and an inorganic, organic SOG, and a polymer when using a ceria slurry. Manufacturing method. 제7항에 있어서, 상기 무기계 SOG로는 하이드로겐 실세스퀴옥산(Hydrogen Silsesquioxane)를 사용하는 것을 특징으로하는 반도체 장치의 제조방법.8. The method of manufacturing a semiconductor device according to claim 7, wherein hydrogen silsesquioxane is used as the inorganic SOG. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960023690A 1996-06-25 1996-06-25 A fabricating method of semiconductor device using cmp process KR100207476B1 (en)

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KR1019960023690A KR100207476B1 (en) 1996-06-25 1996-06-25 A fabricating method of semiconductor device using cmp process

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KR1019960023690A KR100207476B1 (en) 1996-06-25 1996-06-25 A fabricating method of semiconductor device using cmp process

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KR980005733A true KR980005733A (en) 1998-03-30
KR100207476B1 KR100207476B1 (en) 1999-07-15

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