KR980005624A - METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR - Google Patents

METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR Download PDF

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Publication number
KR980005624A
KR980005624A KR1019960025792A KR19960025792A KR980005624A KR 980005624 A KR980005624 A KR 980005624A KR 1019960025792 A KR1019960025792 A KR 1019960025792A KR 19960025792 A KR19960025792 A KR 19960025792A KR 980005624 A KR980005624 A KR 980005624A
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KR
South Korea
Prior art keywords
layer
metal wiring
metal
forming
photoresist pattern
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Application number
KR1019960025792A
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Korean (ko)
Inventor
김태우
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019960025792A priority Critical patent/KR980005624A/en
Publication of KR980005624A publication Critical patent/KR980005624A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 반도체 소자의 금속배선 형성공정에 있어서 셀영역과 주변회로지역의 금속배선을 따로 형성함으로써 셀영역과 주변회로 지역 사이에 형성되는 단차에 의해 금속배선 비등방성 식각시에 금속 잔여물이 남아 금속배선간 단락을 유발하여 반도체 소자의 제조수율을 저하시키는 문제점을 해결할 수 있다.The present invention relates to a method of forming a metal interconnection of a semiconductor device, in which a metal interconnection in a cell region and a peripheral circuit region is separately formed in a metal interconnection forming process of a semiconductor device, The metal residues remain during the anisotropic etching of the wiring to cause a short circuit between the metal wirings, thereby making it possible to solve the problem that the yield of the semiconductor device is lowered.

Description

반도체 소자의 금속배선 형성방법METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2a도 내지 제2d도는 본 발명의 기술에 따른 반도체 소자의 금속배선 형성 공정단계를 도시한 단면도.FIGS. 2a to 2d are cross-sectional views illustrating steps of forming a metal wiring of a semiconductor device according to the technique of the present invention;

Claims (6)

반도체 소자의 금속배선 형성방법에 있어서, 단차가 형성되어 있는 하부 절연 산화막을 상부에 제1금속배선층을 형성하는 단계와, 상기 제1금속배선층의 상부에 소정두께의 제1감광막을 도포한 후 플레이트 전극 마스크를 사용하여 제1감광막 패턴을 형성하는 단계와, 상기 제1감광막 패턴을 식각 마스크로하여 셀영역에 위치한 상기 제1금속배선층을 식각하여 단차가 낮은 주변회로지역에만 제1금속배선층을 남기는 단계와, 상기 주변회로지역에 형성된 제1금속배선층의 상부에 제2감광막을 소정두께로 코팅한 후 제1금속배선 마스크를 사용하여 제2감광막 패턴을 형성하는 단계와, 상기 제2감광막 패턴으로 하부의 제1금속배선층을 비등방성 식각하여 주변회로부 지역에 제1금속배선을 형성하는 단계와, 상기 제2감광막 패턴을 제거한 후, 제2산화막을 소정두께로 증착하는 단계와, 제2산화막의 상부에 제3감광막을 소정두께 코팅한 후 금속배선 콘택 마스크를 사용하여 제3감광막 패턴을 형성하는 단계와, 상기 제3감광막 패턴을 마스크로 사용하여 하부에 제2산화막을 비등방성 식각하여 제2금속배선 콘택홀을 형성하는 단계와, 상기 제3감광막 패턴을 제거한 후 전체구조 상부에 제2금속배선층을 형성하는 단계와, 상기 제2금속배선층 상부에 제4감광막을 소정두께 코팅한 후 셀 지역의 제2금속배선을 형성하기 위하여 제2금속배선 마스크를 사용하여 제4감광막 패턴을 형성하는 단계와, 상기 제4감광막 패턴으로 하부의 제2금속배선층을 비등방성 식각하여 셀 지역에 제2금속배선을 형성하는 단계와 상기 제4감광막 패턴을 제거하는 단계로 구성되는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.A method of forming a metal wiring of a semiconductor device, the method comprising: forming a first metal wiring layer on a lower insulating oxide film on which a step is formed; applying a first photoresist film having a predetermined thickness on the first metal wiring layer; Forming a first photoresist pattern using an electrode mask; etching the first metal interconnection layer located in the cell region using the first photoresist pattern as an etching mask to leave a first metal interconnection layer only in a peripheral circuit region having a low step Forming a second photoresist pattern using a first metal wiring mask after coating a second photoresist layer on a first metal wiring layer formed on the peripheral circuit area to a predetermined thickness; Forming a first metal interconnection in an area of the peripheral circuit by anisotropically etching the first metal interconnection layer at a lower portion of the first metal interconnection layer; Forming a third photoresist pattern by using a metal wiring contact mask after coating the third photoresist layer with a predetermined thickness on top of the second oxide layer; Forming a second metal wiring contact hole by anisotropically etching the second oxide film in a lower portion of the first metal wiring layer, forming a second metal wiring layer on the entire structure after removing the third photoresist pattern, Forming a fourth photoresist pattern by using a second metal interconnection mask to form a second metal interconnection in a cell region after coating a fourth photoresist layer with a predetermined thickness on the first metal layer; Forming a second metal interconnection in an area of the cell by anisotropically etching the interconnection layer; and removing the fourth photoresist pattern. . 제1항에 있어서 상기 제1산화막 상부에 제1금속배선을 증착시킨 후 제1금속 배선 마스크를 사용하여 셀영역과 주변회로지역 금속배선형성을 동시에 진행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method as claimed in claim 1, wherein the first metal wiring is deposited on the first oxide film, and then the metal wiring is formed simultaneously in the cell region and the peripheral circuit region using the first metal wiring mask. Way. 제1항에 있어서 상기 제2산화막의 증착두께는 약 3000Å인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the deposition thickness of the second oxide layer is about 3000 ANGSTROM. 제1항에 있어서 상기 제1감광막으로 네거티브 감광막을 사용하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method according to claim 1, wherein a negative photosensitive film is used as the first photosensitive film. 제1항에 있어서 상기 금속배선간 산화막으로 산화질화막, MTO, HTO, TEOS, 질화막, BPSG중 어느 하나를 사용하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method according to claim 1, wherein any one of an oxide nitride film, MTO, HTO, TEOS, a nitride film, and BPSG is used as the inter-metal wiring oxide film. 제1항에 있어서 상기 제1 및 제2 금속배선은 같은 물질로 사용하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the first and second metal wires are formed of the same material. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960025792A 1996-06-29 1996-06-29 METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR KR980005624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960025792A KR980005624A (en) 1996-06-29 1996-06-29 METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR

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Application Number Priority Date Filing Date Title
KR1019960025792A KR980005624A (en) 1996-06-29 1996-06-29 METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR

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