KR980005445A - Shallow bonding layer formation method on silicon substrate with reduced leakage current - Google Patents

Shallow bonding layer formation method on silicon substrate with reduced leakage current Download PDF

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KR980005445A
KR980005445A KR1019960021802A KR19960021802A KR980005445A KR 980005445 A KR980005445 A KR 980005445A KR 1019960021802 A KR1019960021802 A KR 1019960021802A KR 19960021802 A KR19960021802 A KR 19960021802A KR 980005445 A KR980005445 A KR 980005445A
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South Korea
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ions
silicon substrate
forming
ion implantation
silicon
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KR1019960021802A
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Korean (ko)
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KR100293184B1 (en
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김광일
권영규
배영호
정욱진
Original Assignee
김종진
포항종합제철 주식회사
신장식
재단법인 산업과학기술연구소
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체 소자의 제조방법에 관한 것이며, 그 목적은 게르마늄 혹은 실리콘이온을 주입하여 비정질층을 불순물 이온의 비정거리이상, 접합형성거리 이하까지 형성시켜 누설전류가 적고 실리콘기판에의 양호한 얕은 접합층을 형성하는 방법을 제공함에 있다. 상기 목적달성을 위한 본 발명은 반도체 소자의 제조방법에 있어서, 실리콘 기판에 SiO2산화막을 형성한 후 이온이 주입되는 부위를 에칭제거하는 단계; 상기 이온주입 부위를 통해 불순물(dopant)이온을 주입하기 전에 그 불순물의 비정거리 이상, 접합형성거리 이하의 깊이범위에서 비정질층을 형성하기 위하여 임계 도우즈량 이상의 게르마늄이온 또는 실리콘이온을 1회 이온주입하는 단계; 상기 이온주입 부위를 통하여 기판내에 불순물 이온을 주입하는 단계; 및 질소분위기하에서 급속열처리하여 접합 영역을 형성하는 단계를 포함하여 구성되는 누설전류가 저감되는 실리콘기판에의 얕은 접합층 형성방법에 관한 것을 그 기술적 요지로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and an object thereof is to inject germanium or silicon ions to form an amorphous layer above a certain distance of impurity ions and below a junction formation distance so that a leakage current is low and a good shallow junction to a silicon substrate. A method of forming a layer is provided. In accordance with another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: etching away a portion into which ions are implanted after forming an SiO 2 oxide film on a silicon substrate; Prior to implanting dopant ions through the ion implantation site, a single ion implantation of germanium ions or silicon ions having a critical dose or more in order to form an amorphous layer at a depth range greater than or equal to an impurity and less than a junction formation distance Doing; Implanting impurity ions into the substrate through the ion implantation site; And a method of forming a shallow junction layer on a silicon substrate having a reduced leakage current, which comprises forming a junction region by rapid thermal treatment under a nitrogen atmosphere.

Description

누설전류가 저감되는 실리콘기판에의 얕은 접합층 형성방법Shallow bonding layer formation method on silicon substrate with reduced leakage current

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도 (a) 내지 (d)는 본 발명에 의한 방법을 실시하기 위한 공정의 일예를 단계적으로 나타내는 모식도.1 (a) to (d) are schematic diagrams showing one example of a step for carrying out the method according to the present invention.

Claims (4)

반도체 소자의 제조방법에 있어서, 실리콘 기판에 SiO2산화막을 형성한 후 이온이 주입되는 부위를 에칭제거하는 단계; 상기 이온주입 부위를 통해 불순물 (dopant) 이온을 주입하기 전에 그 불순물의 비정거리 이상, 접합형성거리 이하의 깊이범위에서 비정질층을 형성하기 위하여 임계 도우즈량 이상의 게르마늄이온또는 실리콘이온을 이온주입하는 단계; 상기 이온주입 부위를 통하여 기판내에 불순물 이온을 주입하는 단; 및 질소분위기하에서 급속열처리하여 접합 영역을 형성하는 단계를 포함하여 구성되는 누설전류가 저감되는 실리콘기판에의 얕은 접합층 형성방법.A method of manufacturing a semiconductor device, the method comprising: etching away a portion into which ions are implanted after forming an SiO 2 oxide film on a silicon substrate; Before implanting dopant ions through the ion implantation site, ion implantation of germanium ions or silicon ions of a critical dose or more in order to form an amorphous layer in a depth range greater than or equal to the amorphous distance and less than the junction formation distance ; Implanting impurity ions into the substrate through the ion implantation site; And forming a junction region by rapid heat treatment under a nitrogen atmosphere. 2. A method of forming a shallow junction layer on a silicon substrate, the leakage current of which is configured to be reduced. 제1항에 있어서, 상기 기판은 n형 실리콘 기판이고, 상기 불순물은 붕소(B)임을 특징으로 하는 누설전류가 저감되는 실리콘기판에의 얕은 접합층 형성방법.The method of claim 1, wherein the substrate is an n-type silicon substrate, and the impurity is boron (B). 제1항 또는 제2항에 있어서, 상기 게르마늄 이온 또는 실리콘 이온 주입은 1회만으로 비정질층이 형성되도록 함을 특징으로 하는 누설전류가 저감되는 실리콘기판에의 얕은 접합층 형성방법.3. The method of claim 1 or 2, wherein the germanium ion or silicon ion implantation allows an amorphous layer to be formed only once. 제3항에 있어서, 사이기 게르마늄이온 또는 실리콘이온의 주입을 1×1015/㎠이상의 도우즈량으로 주입하는 누설전류가 저감되는 실리콘기판에의 얕은 접합층 형성방법.4. The method of forming a shallow bonding layer on a silicon substrate according to claim 3, wherein the leakage current is reduced by injecting interstitial germanium ions or silicon ions at a dose of 1 × 10 15 / cm 2 or more. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960021802A 1996-06-17 1996-06-17 Method for forming shallow junction layer on silicon substrate reduced leakage current KR100293184B1 (en)

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