KR970077687A - Ferroelectric RAM for preventing leakage current and manufacturing method thereof - Google Patents

Ferroelectric RAM for preventing leakage current and manufacturing method thereof Download PDF

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KR970077687A
KR970077687A KR1019960017529A KR19960017529A KR970077687A KR 970077687 A KR970077687 A KR 970077687A KR 1019960017529 A KR1019960017529 A KR 1019960017529A KR 19960017529 A KR19960017529 A KR 19960017529A KR 970077687 A KR970077687 A KR 970077687A
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barrier layer
ferroelectric
ferroelectric capacitor
entire surface
insulating film
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KR1019960017529A
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KR100216866B1 (en
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김윤기
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs

누설전류를 방지하기 위한 강유전체 램 및 그 제조방법에 관한 것이다.To a ferroelectric RAM for preventing leakage current and a manufacturing method thereof.

2. 발명이 해결하려고 하는 기술적 과제2. Technical Challenges to be Solved by the Invention

누설전류를 방지하기 위한 강유전체 램 및 그 제조방법에 관한 것이다.To a ferroelectric RAM for preventing leakage current and a manufacturing method thereof.

3. 발명의 해결방법의 요지3. The point of the solution of the invention

기판상에 형성되고 상부 및 하부전극 사이에 강유전체를 가지는 강유전체 커패시터를 적어도 하나 이상을 포함하는 강유전체 램 제조방법에 있어서, 상기 강유전체 커패시터에 발생하는 누설전류를 방지하기 위하여, 그 강유전체 커패시터 전면에 복합 배리어층을 형성하는 제1과정과, 상기 복합 배리어층 전면에 층간절연막을 형성하고, 상기 상부전극 및 하부전극의 상당영역을 에치백으로 개구부를 형성하고, 그 개구부를 중심으로 그 층간절연막 전면에 스페이서막을 형성하고 전류경로를 설정하기 위하여 메탈로 콘택을 형성하는 제2과정으로 이루어지는 것을 요지로 한다.A method for fabricating a ferroelectric RAM, the ferroelectric capacitor including at least one ferroelectric capacitor formed on a substrate and having a ferroelectric material between the upper and lower electrodes. In order to prevent a leakage current generated in the ferroelectric capacitor, Forming an interlayer insulating film on the entire surface of the composite barrier layer; forming an opening in an equivalent area of the upper electrode and the lower electrode by an etch-back and forming a spacer on the entire surface of the interlayer insulating film, And a second step of forming a metal contact to form a film and set a current path.

4. 발명의 중요한 용도4. Important Uses of the Invention

누설전류를 방지하기 위한 강유전체 램 및 그 제조방법에 적합하다.A ferroelectric RAM for preventing leakage current, and a manufacturing method thereof.

Description

누설전류를 방지하기 위한 강유전체 램 및 그 제조방법Ferroelectric RAM for preventing leakage current and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명의 일실시예에 따른 누설전류를 방지하기 위한 강유전체 커패시터를 보여주기 위한 도면.FIG. 2 is a view illustrating a ferroelectric capacitor for preventing a leakage current according to an embodiment of the present invention; FIG.

Claims (15)

기판상에 형성되고, 상부 및 하부전극 사이에 강유전체를 가지는 강유전체 커패시터를 적어도 하나 이상을 포함하는 강유전체 램 제조방법에 있어서 : 상기 강유전체 커패시터에 발생하는 누설전류를 방지하기 위하여, 그 강유전체 커패시터 측벽면과 전면에 복합 배리어층을 형성하는 제1과정과; 상기 복합 배리어층 상에 층간절연막을 형성하고, 상기 상부전극 및 하부전극의 상당영역을 에치백으로 개구부를 형성하고, 그 개구부를 중심으로 그 층간절연막 전면에 스페이서막을 형성하고 전류경로를 설정하기 위하여 메탈로 콘택을 형성하는 제2과정으로 이루어지는 것을 특징으로 하는 강유전체 램 제조방법.A method of manufacturing a ferroelectric RAM comprising at least one ferroelectric capacitor formed on a substrate, the ferroelectric capacitor having a ferroelectric material between upper and lower electrodes, the ferroelectric capacitor comprising: a ferroelectric capacitor; A first process of forming a composite barrier layer on the entire surface; An interlayer insulating film is formed on the composite barrier layer, an opening is formed in a substantial area of the upper electrode and the lower electrode by an etch-back, a spacer film is formed on the entire surface of the interlayer insulating film around the opening, And forming a second ferroelectric layer on the ferroelectric layer. 제1항에 있어서; 상기 복합 배리어층은 산화막 배리어층과 확산 배리어층으로 이루어지는 것을 특징으로 하는 강유전체 램 제조방법.The method of claim 1, further comprising: Wherein the composite barrier layer comprises an oxide barrier layer and a diffusion barrier layer. 제2항에 있어서; 상기 산화막 배리어층은, 산소 이온의 스퍼터링으로 상기 강유전체 커패시터 측벽면과 전면에 약 20Å∼1000Å 두께로 형성되어, 상기 누설전류를 방지하고자 상기 상부전극과 하부전극을 절연시킴을 특징으로 하는 강유전체 램 제조방법.3. The method of claim 2, Wherein the oxide barrier layer is formed to a thickness of about 20 ANGSTROM to 1000 ANGSTROM on the sidewall and the entire surface of the ferroelectric capacitor by sputtering of oxygen ions to insulate the upper electrode and the lower electrode from each other to prevent the leakage current. Way. 제2항에 있어서; 상기 확산 배리어층은 상기 산화막 배리어층 상에 형성되어, 상기 층간절연막과 상기 강유전체 커패시터의 배리어로서 작용하며, 약 50Å∼1000Å의 두께로 형성됨을 특징으로 하는 강유전체 램 제조방법.3. The method of claim 2, Wherein the diffusion barrier layer is formed on the oxide film barrier layer and functions as a barrier between the interlayer dielectric film and the ferroelectric capacitor, and is formed to a thickness of about 50 Å to 1000 Å. 제1항에 있어서; 상기 스페이서막은 산소 이온의 스퍼터링으로 상기 층간절연막 개구부의 측벽 및 전면에 형성되고, 그 단차피복이 약 1:1.5 이상임을 특징으로 하는 강유전체 램 제조방법.The method of claim 1, further comprising: Wherein the spacer film is formed on the sidewalls and the entire surface of the opening of the interlayer insulating film by sputtering of oxygen ions, and the step coverage is about 1: 1.5 or more. 제1항에 있어서; 상기 개구부는 상기 상부전극의 일부표면이 노출되도록 상기 에치백으로 형성됨을 특징으로 하는 강유전체 램 제조방법.The method of claim 1, further comprising: Wherein the opening is formed in the etch-back so that a part of the surface of the upper electrode is exposed. 기판상에 형성된 강유전체 램에 있어서; 상부전극과 하부전극 사이에 강유전체가 형성되고, 그 상부전극에 형성되어 누설전류를 억제하기 위한 복합 배리어층과; 그 복합 배리어층의 상부에 형성되고, 메탈을 형성하기 위한 개구부를 가지며, 그 개구부에 의해 이격된 층간절연막으로 이루어진 강유전체 커패시터를 적어도 하나 이상을 포함하는 것을 특징으로 하는 강유전체 램.A ferroelectric RAM formed on a substrate, comprising: A composite barrier layer formed between the upper electrode and the lower electrode to form a ferroelectric and formed on the upper electrode to suppress a leakage current; And a ferroelectric capacitor formed on the composite barrier layer and having an opening for forming a metal, the ferroelectric capacitor comprising an interlayer insulating film spaced apart by the opening. 제7항에 있어서; 상기 복합 배리어층은 산소 이온의 저 온도로 스퍼터링된 산화막 배리어층과, 그 산화막 배리어층 전면에 형성된 티타늄으로 이루어진 확산 배리어층으로 이루어지는 것을 특징으로 하는 강유전체 램.8. The method of claim 7, further comprising: Wherein the composite barrier layer comprises an oxide film barrier layer sputtered at a low temperature of oxygen ions and a diffusion barrier layer made of titanium formed on the entire surface of the oxide film barrier layer. 제7항에 있어서; 상기 층간절연막은 산소 이온의 스퍼터링으로 저 온도에서 형성됨을 특징으로 하는 강유전체 램.8. The method of claim 7, further comprising: Wherein the interlayer dielectric layer is formed at a low temperature by sputtering oxygen ions. 제7항에 있어서; 상기 층간절연막은 그 전면에 스페이서로 이용될 절연막을 더 가짐을 특징으로 하는 강유전체 램.8. The method of claim 7, further comprising: Wherein the interlayer insulating film further has an insulating film to be used as a spacer on the entire surface thereof. 제7항에 있어서; 상기 개구부는 상기 상부전극의 표면일부가 노출되도록 에치백에 의해 이루어지고, 그 단차피복이 약 1:1.5 이상임을 특징으로 하는 강유전체 램.8. The method of claim 7, further comprising: Wherein the opening is formed by an etch-back so that a part of the surface of the upper electrode is exposed, and the step coverage is about 1: 1.5 or more. 강유전체 램 제조방법에 있어서 : 상부전극 및 하부전극 사이에 강유전성 물질을 형성하여 강유전체 커패시터를 형성하고 그 강유전체 커패시터에 발생하는 누설전류를 방지하기 위하여, 그 강유전체 커패시터 전면에 산화막 배리어층과 확산 배리어층을 차례로 형성하는 제1과정과; 상기 확산 배리어층 전면에 층간절연막을 형성하고, 상기 상부전극 및 하부전극의 상당영역을 에치백으로 개구부를 형성하고, 그 개구부를 중심으로 그 층간절연막 전면에 스페이서막을 형성하고 전류경로를 설정하기 위하여 메탈로 콘택을 형성하는 제2과정으로 이루어지는 것을 특징으로 하는 강유전체 램 제조 방법.A method of manufacturing a ferroelectric RAM, comprising the steps of: forming a ferroelectric capacitor between a top electrode and a bottom electrode to form a ferroelectric capacitor and to prevent a leakage current generated in the ferroelectric capacitor, an oxide barrier layer and a diffusion barrier layer are formed over the ferroelectric capacitor A first step of sequentially forming the first electrode and the second electrode; An interlayer insulating film is formed on the entire surface of the diffusion barrier layer, an opening is formed in a substantial area of the upper electrode and the lower electrode by an etch-back, a spacer film is formed on the entire surface of the interlayer insulating film, And forming a second ferroelectric layer on the ferroelectric layer. 불휘발성 강유전체 커패시터를 가지는 강유전체 램에 있어서; 상기 강유전체 커패시터의 누설전류를 방지하기 위하여 그 강유전체 전면에 복합 배리어층을 가짐을 특징으로 하는 강유전체 램.A ferroelectric RAM having a nonvolatile ferroelectric capacitor, comprising: Wherein a ferroelectric capacitor has a composite barrier layer on the entire surface of the ferroelectric capacitor to prevent leakage current of the ferroelectric capacitor. 제13항에 있어서; 상기 복합 배리어층은 약 20Å∼1000Å 두께의 산소 이온의 스퍼터링으로 형성된 산화막 배리어층과, 약 50Å∼1000Å 두께의 티타늄으로 형성된 확산 배리어층으로 이루어지는 것을 특징으로 하는 강유전체 램.14. The method of claim 13, Wherein the composite barrier layer comprises an oxide barrier layer formed by sputtering oxygen ions of about 20 ANGSTROM to about 1000 ANGSTROM and a diffusion barrier layer formed of about 50 ANGSTROM to about 1000 ANGSTROM thick. 제13항에 있어서; 상기 복합 배리어층은, 그 상부에 낮은 온도로 스퍼터링에 의해 형성된 층간절연막을 더 가짐을 특성으로 하는 강유전체 램.14. The method of claim 13, Wherein the composite barrier layer further has an interlayer insulating film formed thereon by sputtering at a low temperature. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960017529A 1996-05-22 1996-05-22 Ferroelectric ram for preventing leakage currents and its manufacturing method KR100216866B1 (en)

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KR100362179B1 (en) * 1999-12-30 2002-11-23 주식회사 하이닉스반도체 Semiconductor memory device having oxide and Ti double layer capable of preventing hydrogen diffusion and method for forming the same
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