KR970072222A - Method of arranging a pin pad of a semiconductor integrated circuit - Google Patents

Method of arranging a pin pad of a semiconductor integrated circuit Download PDF

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Publication number
KR970072222A
KR970072222A KR1019960010366A KR19960010366A KR970072222A KR 970072222 A KR970072222 A KR 970072222A KR 1019960010366 A KR1019960010366 A KR 1019960010366A KR 19960010366 A KR19960010366 A KR 19960010366A KR 970072222 A KR970072222 A KR 970072222A
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KR
South Korea
Prior art keywords
pin
chip
integrated circuit
semiconductor integrated
pin pad
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KR1019960010366A
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Korean (ko)
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KR100224657B1 (en
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조병환
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김광호
삼성전자 주식회사
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Priority to KR1019960010366A priority Critical patent/KR100224657B1/en
Publication of KR970072222A publication Critical patent/KR970072222A/en
Application granted granted Critical
Publication of KR100224657B1 publication Critical patent/KR100224657B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

반도체 집적회로의 병렬 웨이퍼 테스트를 위한 핀 패드(pin pad) 배치방법을 개시한다.A pin pad arrangement method for parallel wafer testing of a semiconductor integrated circuit is disclosed.

반도체 집적회로의 핀 패드(pin pad) 배치방법에 있어서, 칩(chip)의 서로 마주보고 있는 양측면에 핀 패드(pin pad)가 각각 한겹 또는 두겹으로 배치됨을 특징으로 한다.In a method of arranging a pin pad of a semiconductor integrated circuit, pin pads are disposed on both sides of the chip facing each other in one or two layers.

따라서, 칩의 병렬 테스트가 가능하도록 함으로써, 생산성 향상의 효과를 제공한다.Therefore, parallel testing of chips is made possible, thereby providing an effect of improving productivity.

Description

반도체 집적회로의 핀 패드(pin pad) 배치방법Method of arranging a pin pad of a semiconductor integrated circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제4A도는 본 발명에 따른 칩내의 핀 배치방법의 일실시예를 보이는 도면이고, 제4B도는 제4A도에 따른 병렬프로우빙 방식을 보이는 단면도이다.FIG. 4A is a view showing one embodiment of a pin arrangement method in a chip according to the present invention, and FIG. 4B is a cross-sectional view showing a parallel probing method according to FIG.

Claims (10)

반도체 집적회로의 핀 패드(pin pad) 배치방법에 있어서, 칩(chip)의 서로 마주보고 있는 양측면에 핀 패드(pin pad)가 각각 한겹으로 배치됨을 특징으로 하는 반도체 직접회로의 핀 패드(pin pad) 배치방법.A method of arranging a pin pad of a semiconductor integrated circuit, wherein pin pads are disposed on both sides of the chip facing each other, ) Placement method. 제1항에 있어서, 상기 칩(chip)의 가로측의 상단부와 하단부에 각각 한겹으로 핀 패드(pin pad)가 배치됨을 특징으로 하는 반도체 집적회로의 핀 패드(pin pad) 배치방법.The method as claimed in claim 1, wherein a pin pad is disposed on one side of each of the upper and lower ends of the chip. 제1항에 있어서, 상기 칩(chip)의 세로측의 좌단부와 우단부에 각각 한겹으로 핀 패드(pin pad)가 배치됨을 특징으로 하는 반도체 집적회로의 핀 패드(pin pad) 배치방법.The method as claimed in claim 1, wherein a pin pad is disposed on a left side and a right side of a longitudinal side of the chip, respectively. 제2항 내지 제3항에 있어서, 상기 각각의 모서리에 위치하는 4개의 핀 패드들은 그 외의 핀 패드들보다 칩 중앙에 배치됨을 특징으로 하는 반도체 직접회로의 핀 패드(pin pad) 배치방법.4. The method of claim 2, wherein the four pin pads located at the respective corners are disposed at the center of the chip rather than the other pin pads. 제2항 내지 제3항에 있어서, 상기 각각의 핀 패드들은 이웃하는 핀 패드와 단차를 가지며 소정의 곡률을 갖도록 배치됨을 특징으로 하는 반도체 직접회로의 핀 패드(pin pad) 배치방법.The method of claim 2, 3 or 4, wherein each of the plurality of pin pads has a step with the neighboring pin pads and has a predetermined curvature. 반도체 집적회로의 핀 패드(pin pad) 배치방법에 있어서, 칩(chip)의 서로 마주보고 있는 양측면에 핀 패드(pin pad) 가 각각 두겹으로 배치됨을 특징으로 하는 반도체 집적회로의 핀 패드(pin pad) 배치 방법.A method of disposing a pin pad of a semiconductor integrated circuit, the method comprising the steps of: forming a plurality of pin pads on opposite sides of the chip, ) Placement method. 제6항에 있어서, 상기 칩(chip)의 가로측의 상단부와 하단부에 각각 두겹으로 핀 패드(pin pad) 가 배치됨을 특징으로 하는 반도체 집적회로의 핀 패드(pin pad) 배치 방법.The method as claimed in claim 6, wherein a pin pad is arranged in two layers at an upper end and a lower end of a lateral side of the chip. 제6항에 있어서, 상기 칩(chip)의 세로측의 좌단부와 우단부에 각각 두겹으로 핀 패드(pin pad) 가 배치됨을 특징으로 하는 반도체 집적회로의 핀 패드(pin pad) 배치 방법.7. The method of claim 6, wherein a pin pad is disposed in two layers on the left and right ends of the vertical side of the chip. 제7항 내지 제8항에 있어서, 상기 각각의 모서리에 위치하는 8개의 핀 패드들은 그 외의 핀 패드들보다 칩 중앙에 배치됨을 특징으로 하는 반도체 집적회로의 핀 패드(pin pad) 배치방법.9. The method of claim 7, wherein the eight pin pads located at the respective corners are disposed at the center of the chip rather than the other pin pads. 제7항 내지 제8항에 있어서, 상기 각각의 핀 패드들은 이웃하는 핀 패드와 단차를 가지며 소정의 곡률을 갖도록 배치됨을 특징으로 하는 반도체 직접회로의 핀 패드(pin pad) 배치방법.9. The method of claim 7, wherein each of the plurality of pin pads has a step with the neighboring pin pads and has a predetermined curvature. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960010366A 1996-04-06 1996-04-06 Pin pad display method of semiconductor ic KR100224657B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960010366A KR100224657B1 (en) 1996-04-06 1996-04-06 Pin pad display method of semiconductor ic

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Application Number Priority Date Filing Date Title
KR1019960010366A KR100224657B1 (en) 1996-04-06 1996-04-06 Pin pad display method of semiconductor ic

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KR970072222A true KR970072222A (en) 1997-11-07
KR100224657B1 KR100224657B1 (en) 1999-10-15

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Publication number Priority date Publication date Assignee Title
JPS5546578A (en) * 1978-09-30 1980-04-01 Toshiba Corp Method of mounting integrated circuit

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