KR100224657B1 - Pin pad display method of semiconductor ic - Google Patents

Pin pad display method of semiconductor ic Download PDF

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KR100224657B1
KR100224657B1 KR1019960010366A KR19960010366A KR100224657B1 KR 100224657 B1 KR100224657 B1 KR 100224657B1 KR 1019960010366 A KR1019960010366 A KR 1019960010366A KR 19960010366 A KR19960010366 A KR 19960010366A KR 100224657 B1 KR100224657 B1 KR 100224657B1
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chip
pin
pads
pin pad
parallel
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KR1019960010366A
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KR970072222A (en
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조병환
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윤종용
삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

반도체 집적회로의 병렬 웨이퍼 테스트를 위한 핀 패드(pin pad) 배치방법 을 개시한다.A method of pin pad placement for parallel wafer testing of semiconductor integrated circuits is disclosed.

반도체 집적회로의 핀 패드(pin pad) 배치방법에 있어서, 칩(chip)의 서로 마주보고 있는 양측면에 핀 패드(pin pad)가 각각 한겹 또는 두겹으로 배치됨을 특징으로 한다.In a pin pad arrangement method of a semiconductor integrated circuit, pin pads are disposed in one or two layers on both sides of the chip facing each other.

따라서, 칩의 병렬 테스트가 가능하도록 함으로써, 생산성 향상의 효과를 제공한다.Thus, by enabling parallel testing of the chips, the effect of improving productivity is provided.

Description

반도체 집적회로의 핀 패드(pin pad) 배치방법Pin pad arrangement method of semiconductor integrated circuit

제1도는 종래 기술의 반도체 집적회로의 핀 패드(pin pad) 배치방법을 도시한 도면이다.1 is a view showing a pin pad arrangement method of a semiconductor integrated circuit of the prior art.

제2도는 일반적인 싱글 칩 프로우빙(single chip probing) 방식을 보이 는 도면 이다.2 is a diagram showing a general single chip probing method.

제3도는 일반적인 듀얼-칩(Dual-Chip) 프로우빙 방식을 보이는 도면이다.3 is a diagram illustrating a general dual-chip probing method.

제4a도는 본 발명에 따른 칩내의 핀 배치방법의 일실시예를 보이는 도면이고, 제4b도는 제4a도에 따른 병렬 프로우빙 방식을 보이는 도면이다.Figure 4a is a view showing an embodiment of the pin arrangement method in the chip according to the present invention, Figure 4b is a view showing a parallel probing method according to Figure 4a.

제5a도는 본 발명에 따른 칩내의 핀 배치방법의 다른 일실시예를 보이는 도면이고, 제5b도는 제5a도에 따른 병렬 프로우빙 방식을 보이는 도면이다.Figure 5a is a view showing another embodiment of the pin arrangement method in the chip according to the present invention, Figure 5b is a view showing a parallel probing method according to Figure 5a.

제6a도는 본 발명에 따른 칩내의 핀 배치방법의 또 다른 일실시예를 보이는 도면이고, 제6b도는 제6a도에 따른 병렬 프로우빙 방식을 보이는 도면이다 .FIG. 6A is a view showing another embodiment of a pin arrangement method in a chip according to the present invention, and FIG. 6B is a view showing a parallel probing method according to FIG. 6A.

제7a도는 본 발명에 따른 칩내의 핀 배치방법의 또 다른 일실시예를 보이는 도면이고, 제7b도는 제7a도에 따른 병렬 프로우빙 방식을 보이는 도면이다.FIG. 7a illustrates another embodiment of a pin arrangement method in a chip according to the present invention, and FIG. 7b illustrates a parallel probing method according to FIG. 7a.

제8a도는 본 발명에 따른 칩내의 핀 배치방법의 또 다른 일실시예를 보이는 도면이고, 제8b도는 제8a도에 따른 병렬 프로우빙 방식을 보이는 도면이다.FIG. 8a illustrates another embodiment of a pin arrangement method in a chip according to the present invention, and FIG. 8b illustrates a parallel probing method according to FIG. 8a.

제9a도는 본 발명에 따른 칩내의 핀 배치방법의 또 다른 일실시예를 보이는 도면이고, 제9b도는 제9a도에 따른 병렬 프로우빙 방식을 보이는 도면이다.Figure 9a is a view showing another embodiment of the pin arrangement method in the chip according to the present invention, Figure 9b is a view showing a parallel probing method according to Figure 9a.

제10a도는 본 발명에 따른 칩내의 핀 배치방법의 또 다른 일실시예를 보이는 도면이고, 제10b도는 제10a도에 따른 병렬 프로우빙 방식을 보이는 도면이다.FIG. 10A illustrates another embodiment of a pin arrangement method in a chip according to the present disclosure, and FIG. 10B illustrates a parallel probing method according to FIG. 10A.

제11a도는 본 발명에 따른 칩내의 핀 배치방법의 또 다른 일실시예를 보이는 도면이고, 제11b도는 제11a도에 따른 병렬 프로우빙 방식을 보이는 도면이다.FIG. 11A illustrates another embodiment of a pin arrangement method in a chip according to the present invention, and FIG. 11B illustrates a parallel probing method according to FIG. 11A.

본 발명은 반도체 설비에 관한 것으로서, 특히 반도체 집적회로의 병렬 웨이퍼 테스트를 위한 핀 패드(pin pad) 배치방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor equipment and, more particularly, to a pin pad placement method for parallel wafer testing of semiconductor integrated circuits.

일반적으로, 반도체 집적회로의 핀 레이아웃(pin layout) 구조는 제1도에서 보이는 바와 같이 칩(chip)의 바깥쪽(four sides)을 모두 이용하여 설계된다.In general, the pin layout structure of a semiconductor integrated circuit is designed using all four sides of the chip as shown in FIG.

제1도를 참조하면, 참조부호 100은 반도체 웨이퍼(wafer)이고. 102는 반도체 웨이퍼(100)를 구성하는 하나의 칩(chip)이며, 104는 칩(102)의 핀 패드(pin pad)이다.Referring to FIG. 1, reference numeral 100 denotes a semiconductor wafer. 102 is one chip constituting the semiconductor wafer 100, and 104 is a pin pad of the chip 102.

상술한 바와 같은 구조는 반도체 칩을 각각 테스트하기에는 유용한 구조를 갖는다.The structure as described above has a structure useful for testing each semiconductor chip.

제2도는 싱글 칩 프로우빙(single chip probing) 방식을 보이는 도면이다. 제2도에서 보인 바와 같은 싱글 칩 프로우빙(single chip probing) 방식은 각각의 반도체 칩을 테스트하기에는 매우 유용하다. 그러나, 싱글 칩 프로우빙(single chip probing) 방식은 멀티-사이츠(병렬)(Multi-Sites(parallel)) 테스트를 수행하는 용도로는 매우 취약한 구조가 된다. 이 구조로 멀티-사이츠(병렬), ( Multi-Sites(parallel)) 테스트를 수행하더라도 듀얼-사이츠(Dual-Sites(Two Parallel)) 테스트 밖에 할 수가 없다. 이는 웨이퍼 칩(wafer chip)과 프로우브 카드의 물리적인 구조에 의하여 프로우브 팁(probe tip)의 배열은 제3도에서 보이는 바와 같은 듀얼-칩(Dual-Chip) 프로우빙 방식에서 탈피할 수가 없기 때문이다.2 is a diagram showing a single chip probing method. The single chip probing scheme as shown in FIG. 2 is very useful for testing each semiconductor chip. However, the single chip probing method is a very vulnerable structure for performing multi-sites (parallel) test. Even with the multi-sites (parallel) test with this structure, you can only do dual-sites (two parallel) tests. Due to the physical structure of the wafer chip and probe card, the arrangement of probe tips cannot be avoided from the dual-chip probing method as shown in FIG. Because.

이를 해결하기 위한 방법으로 프로우브 카드의 프로우빙 방식을 3차원 구조로 취하는 방식을 생각해 볼 수 있으나, 이는 현실적으로 매우 어려운 방법이다. 왜냐하면, 프로우브 카드의 3차원 제작 기술이 전무하기 때문이다. 또한, 현재의 프로우브 카드로는 구조적으로 3차원 구조가 어렵게 되어있다.As a way to solve this problem, it is possible to think of a probing method of a probe card as a three-dimensional structure, but this is a very difficult method in reality. This is because there is no 3D production technology of the probe card. In addition, the three-dimensional structure of the present probe card is difficult.

따라서, 본 발명 목적은 상술한 바와 같은 종래 기술의 문제점을 개선하기 위하여 안출된 것으로서 프로우브 카드의 2차원 구조를 그대로 이용하면서 멀티-사이츠(병렬), (multi-sites(parallel)) 테스트가 가능하도록 하는 핀(pin) 배치방법을 제공함에 있다.Accordingly, an object of the present invention is to solve the problems of the prior art as described above, and the multi-sites (parallel) test can be performed while using the two-dimensional structure of the probe card as it is. It is to provide a pin arrangement method to enable.

상술한 바와 같은 목적을 달성하기 위한 반도체 집적회로의 병렬 웨이퍼 테스트를 위한 핀(pin) 배치방법의 일실시예는One embodiment of a pin placement method for parallel wafer testing of a semiconductor integrated circuit to achieve the above object is

반도체 집적회로의 핀 패드(pin pad) 배치 방법에 있어서,In the pin pad arrangement method of a semiconductor integrated circuit,

칩(chip)의 서로 마주보고 있는 양측면에 핀 패드(pin pad)가 각각 한겹으로 배치됨을 특징으로 한다.Pin pads are disposed on both sides of the chip facing each other in a single layer.

상기 칩(chip)의 가로측의 상단부와 하단부에 각각 한겹으로 핀 패드(pin pad)가 배치됨이 바람직하다.It is preferable that pin pads are arranged in one layer on each of the upper and lower ends of the horizontal side of the chip.

또한, 상기 칩(chip)의 세로측의 좌단부와 우단부에 각각 한겹으로 핀 패드(pin pad)가 배치됨이 바람직하다.In addition, it is preferable that pin pads are arranged in one layer on the left end and the right end of the vertical side of the chip.

또한, 상기 각각의 모서리에 위치하는 4개의 핀 패드들은 그 외의 핀 패드들보다 칩 중앙체 배치됨이 바람직하다.In addition, it is preferable that the four pin pads positioned at each corner are disposed on the chip center rather than the other pin pads.

또한, 상기 각각의 핀 패드들은 이웃하는 핀 패드와 단차를 가지며 소정의 곡률을 갖도록 배치됨이 바람직하다.In addition, each of the pin pads is preferably arranged to have a predetermined curvature and a step with the neighboring pin pad.

본 발명에 따른 다른 실시예는Another embodiment according to the present invention

반도체 집적회로의 핀 패드(pin pad) 배치 방법에 있어서,In the pin pad arrangement method of a semiconductor integrated circuit,

칩(chip)의 서로 마주보고 있는 양측면에 핀 패드(pin pad)가 각각 두겹으로 배치됨을 특징으로 한다.A pin pad is disposed in two layers on both sides of the chip facing each other.

상기 칩(chip)의 가로측의 상단부와 하단분에 각각 두겹으로 핀 패드(pin pad)가 배치됨이 바람직하다.Preferably, a pin pad is disposed in two layers at the upper end and the lower end of the horizontal side of the chip.

또한, 상기 칩(chip)의 세로측의 좌단부와 우단부에 각각 두겹으로 핀 패드(pin pad)가 배치됨이 바람직하다.In addition, it is preferable that pin pads are disposed in two layers at the left end and the right end of the vertical side of the chip, respectively.

또한, 상기 각각의 모서리에 위치하는 8개의 핀 패드들은 그 외의 핀 패드들보다 칩 중앙에 배치됨이 바람직하다.In addition, it is preferable that the eight pin pads positioned at each corner are disposed at the center of the chip rather than the other pin pads.

또한, 상기 각각의 핀 패드들은 이웃하는 핀 패드와 단차를 가지며 소정의 곡률을 갖도록 배치됨이 바람직하다.In addition, each of the pin pads is preferably arranged to have a predetermined curvature and a step with the neighboring pin pad.

이하, 첨부된 도면을 참조하여 본 발명을 보다 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

제4a도는 본 발명에 따른 칩내의 핀 배치방법의 일실시예를 보이는 도면이고, 제4b도는 제4a도에 따른 병렬 프로우빙 방식을 보이는 도면이다.Figure 4a is a view showing an embodiment of the pin arrangement method in the chip according to the present invention, Figure 4b is a view showing a parallel probing method according to Figure 4a.

제4a도를 참조하면, 칩(400)의 가로측의 상단부와 하단부에 각각 일겹으로 핀 패드(402)를 배치한다.Referring to FIG. 4A, the pin pads 402 are disposed in one layer on the upper and lower ends of the horizontal side of the chip 400.

제4b도를 참조하면, 제4a도와 같은 핀 패드의 배치의 경우에 있어서 병렬 프로우빙 방식을 보이는 도면이다. 제4b도에 있어서, 404는 프로우브 팁이다.Referring to FIG. 4B, a parallel probing method is shown in the case of the arrangement of the pin pad as shown in FIG. 4A. In FIG. 4B, 404 is a probe tip.

제5a도는 본 발명에 따른 칩내의 핀 배치방법의 다른 일실시예를 보이는 도면이고, 제5b도는 제5a도에 따른 병렬 프로우빙 방식을 보이는 도면이다.Figure 5a is a view showing another embodiment of the pin arrangement method in the chip according to the present invention, Figure 5b is a view showing a parallel probing method according to Figure 5a.

제5a도를 참조하면, 칩(400)의 가로측의 상단부와 하단부에 각각 이겹으로 핀 패드(402)를 배치한다.Referring to FIG. 5A, the pin pads 402 are disposed in double layers at upper and lower ends of the horizontal side of the chip 400.

제5b도를 참조하면, 제5a도와 같은 핀 패드의 배치의 경우에 있어서 병렬 프로우빙 방식을 보이는 도면이다.Referring to FIG. 5B, a parallel probing method is shown in the case of the arrangement of the pin pad as shown in FIG. 5A.

제6a도는 본 발명에 따른 칩내의 핀 배치방법의 또 다른 일실시예를 보이는 도면이고, 제6b도는 제6a도에 따른 병렬 프로우빙 방식을 보이는 도면이다.FIG. 6a illustrates another embodiment of a pin arrangement method in a chip according to the present invention, and FIG. 6b illustrates a parallel probing method according to FIG. 6a.

제6a도를 참조하면, 칩(400)의 세로측의 좌단부와 우단부에 각각 일겹으로 핀 패드(402)를 배치한다.Referring to FIG. 6A, the pin pads 402 are disposed in one layer on the left end and the right end of the chip 400, respectively.

제6b도를 참조하면, 제6a도와 같은 핀 패드의 배치의 경우에 있어서 병렬 프로우빙 방식을 보이는 도면이다.Referring to FIG. 6B, a parallel probing method is shown in the case of the arrangement of the pin pad as shown in FIG. 6A.

제7a도는 본 발명에 따른 칩내의 핀 배치방법의 또 다른 일실시예를 보이는 도면이고, 제7b도는 제7a도에 따른 병렬 프로우빙 방식을 보이는 도면이다.FIG. 7a illustrates another embodiment of a pin arrangement method in a chip according to the present invention, and FIG. 7b illustrates a parallel probing method according to FIG. 7a.

제7a도를 참조하면, 칩(400)의 세로측의 좌단부와 우단부에 각각 이겹으로 핀 패드(402)를 배치한다.Referring to FIG. 7A, the pin pads 402 are disposed in two layers at the left end and the right end of the chip 400, respectively.

제7b도를 참조하면, 제7a도와 같은 핀 패드의 배치의 경우에 있어서 병렬 프로우빙 방식을 보이는 도면이다.Referring to FIG. 7B, a parallel probing method is shown in the case of the arrangement of the pin pad as shown in FIG. 7A.

제8a도는 본 발명에 따른 칩내의 핀 배치방법의 또 다른 일실시예를 보이는 도면이고, 제8b도는 제8a도에 따른 병렬 프로우빙 방식을 보이는 도면이다.FIG. 8a illustrates another embodiment of a pin arrangement method in a chip according to the present invention, and FIG. 8b illustrates a parallel probing method according to FIG. 8a.

제8a도를 참조하면, 칩(400)의 가로측의 상단부와 하단부에 각각 일겹으로 핀 패드(402)를 배치하며, 가로측의 상단부 및 하단부 각각의 모서리에 위치하는 4개의 핀 패드들은 그 외의 핀 패드들보다 칩 중앙에 배치한다.Referring to FIG. 8A, the pin pads 402 are disposed in one layer on each of the upper and lower portions of the horizontal side of the chip 400, and the four pin pads positioned at the corners of the upper and lower portions of the horizontal side are different. It is placed in the center of the chip rather than pin pads.

제8b도를 참조하면, 제8a도와 같은 핀 패드의 배치의 경우에 있어서 병렬 프로우빙 방식을 보이는 도면이다.Referring to FIG. 8B, a parallel probing method is shown in the case of the arrangement of the pin pad as shown in FIG. 8A.

제9a도는 본 발명에 따른 칩내의 핀 배치방법의 또 다른 일실시예를 보이는 도면이고, 제9b도는 제9a도에 따른 병렬 프로우빙 방식을 보이는 도면이다.Figure 9a is a view showing another embodiment of the pin arrangement method in the chip according to the present invention, Figure 9b is a view showing a parallel probing method according to Figure 9a.

제9a도를 참조하면, 칩(400)의 가로측의 상단부와 하단부에 각각 일겹으로 핀 패드(402)를 배치하며, 가로측의 상단부 및 하단부 각각의 핀 패드(402)들을 소정의 곡률을 갖도록 배치한다.Referring to FIG. 9A, the pin pads 402 are disposed in one layer on the upper and lower ends of the horizontal side of the chip 400, and the pin pads 402 of the upper and lower ends of the horizontal side have a predetermined curvature. To place.

제9b도를 참조하면, 제9a도와 같은 핀 패드의 배치의 경우에 있어서 병렬 프로우빙 방식을 보이는 도면이다.Referring to FIG. 9B, a parallel probing method is shown in the case of the arrangement of the pin pad as shown in FIG. 9A.

제10a도는 본 발명에 따른 칩내의 핀 배치방법의 또 다른 일실시예를 보이는 도면이고, 제10b도는 제10a도에 따른 병렬 프로우빙 방식을 보이는 도면이다.FIG. 10A illustrates another embodiment of a pin arrangement method in a chip according to the present disclosure, and FIG. 10B illustrates a parallel probing method according to FIG. 10A.

제10a도를 참조하면, 칩(400)의 세로측의 좌단부와 우단부에 각각 일겹으로 핀 패드(402)를 배치하며, 세로측의 좌단부 및 우단부 각각의 모서리에 위치하는 4개의 핀 패드들은 그 외의 핀 패드들보다 칩 중앙에 배치한다.Referring to FIG. 10A, the pin pads 402 are disposed in one layer on the left end and the right end of the vertical side of the chip 400, and the four pin pads positioned at the corners of the left and right ends of the vertical side, respectively. It is placed in the center of the chip more than other pin pads.

제10b도를 참조하면, 제10a도와 같은 핀 패드의 배치의 경우에 있어서 병렬 프로우빙 방식을 보이는 도면이다.Referring to FIG. 10B, a parallel probing method is shown in the case of the arrangement of the pin pad as shown in FIG. 10A.

제11a도는 본 발명게 따른 칩내의 핀 배치방법의 또 다른 일실시예를 보이는 도면이고, 제11b도는 제11a도에 따른 병렬 프로우빙 방식을 보이는 도면이다.FIG. 11a is a view showing another embodiment of a pin arrangement method in a chip according to the present invention, and FIG. 11b is a view showing a parallel probing method according to FIG. 11a.

제11a도를 참조하면, 칩(400)의 세로측의 좌단부와 우단부에 각각 일겹으로 핀 패드(402)를 배치하며, 세로측의 좌단부 및 우단부 각각의 핀 패드(402)들을 소정의 곡률을 갖도록 배치한다.Referring to FIG. 11A, the pin pads 402 are arranged in one layer on the left end and the right end of the vertical side of the chip 400, and the pin pads 402 of the left and right ends of the vertical side are respectively given a predetermined curvature. Arrange to have.

제11b도를 참조하면, 제11a도와 같은 핀 패드의 배치의 경우에 있어서 병렬 프로우빙 방식을 보이는 도면이다.Referring to FIG. 11B, a parallel probing method is shown in the case of the arrangement of the pin pad as shown in FIG. 11A.

상술한 바와 같은 반도체 집적회로의 핀 패드(pin pad) 배치방법은 칩의 병렬 테스트가 가능하도록 함으로써, 생산성 향상의 효과를 제공한다.The pin pad arrangement method of the semiconductor integrated circuit as described above enables the parallel test of the chip, thereby providing an effect of improving productivity.

Claims (5)

반도체 집적회로의 핀 패드(pin pad) 배치방법에 있어서,In a pin pad arrangement method of a semiconductor integrated circuit, 칩의(chip)의 서로 마주보고 있는 양측면에 핀 패드(pin pad)가 각각 한겹으로 배치되고,Pin pads are arranged in one layer on both sides of the chip facing each other, 상기 마주보고 있는 양측면은 상기 칩(chile)의 가로축 상단부와 하단부이거나, 상기 칩의 세로축 좌단부와 우단부이며,The opposite sides facing each other are the upper and lower ends of the horizontal axis of the chip, or the left end and the right end of the vertical axis of the chip. 상기 칩의 각 모서리에 위치하는 4개의 핀 패드들은 그 이외의 핀 패드들보다 칩 중앙을 향하여 소정 간격 근접하게 배치되는 것을 특징으로 하는 반도체 집적 회로의 핀 패드 배치 방법.Four pin pads positioned at each corner of the chip are disposed closer to the center of the chip than the other pin pads by a predetermined distance. 제1항에 있어서, 상기 각각의 핀 패드들은 좌우측의 인접 패드들과 단차를 가지며 소정의 곡률을 갖도록 배치됨을 특징으로 하는 반도체 집적회로의 핀 패드(pin pad) 배치방법.The pin pad arrangement method of claim 1, wherein each of the pin pads is disposed to have a predetermined curvature and a step with adjacent pads on the left and right sides. 반도체 집적회로의 핀 패드(pin pad) 배치 방법에 있어서,In the pin pad arrangement method of a semiconductor integrated circuit, 칩(chip)의 서로 마주보고 있는 양측면에 핀 패드(pin pad)들이 각각 두겹으로 배치되고,Pin pads are arranged in two layers on both sides of the chip facing each other, 상기 마주보고 있는 양측면은 상기 칩(chip)의 가로축 상단부와 하단부이거나, 상기 칩의 세로축 좌단부와 우단부인 것을 특징으로 하는 반도체 집적회로의 핀 패드(pin pad) 배치방법.The opposite side surfaces facing each other are the upper and lower ends of the horizontal axis of the chip, or the left and right ends of the vertical axis of the chip. 제3항에 있어서, 상기 각각의 모서리에 위치하는 8개의 핀 패드들은 그 외의 핀 패드들보다 칩 중앙을 향하여 소정 간격 근접하게 배치됨을 특징으로 하는 반도체 집적회로의 핀 패드(pin pad) 배치방법.4. The method of claim 3, wherein the eight pin pads positioned at each corner are disposed closer to each other toward the center of the chip than the other pin pads. 제4항에 있어서, 상기 각각의 핀 패드들은 좌우측의 인접 패드들과 단차를 가지며 소정의 곡률을 갖도록 배치됨을 특징으로 하는 반도체 집적회로의 핀 패드(pin pad) 배치방법.5. The method of claim 4, wherein each of the pin pads is disposed to have a predetermined curvature and a step with adjacent left and right adjacent pads. 6.
KR1019960010366A 1996-04-06 1996-04-06 Pin pad display method of semiconductor ic KR100224657B1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5546578A (en) * 1978-09-30 1980-04-01 Toshiba Corp Method of mounting integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5546578A (en) * 1978-09-30 1980-04-01 Toshiba Corp Method of mounting integrated circuit

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