KR970068369A - High-level data communication control (HDLC) communication device - Google Patents

High-level data communication control (HDLC) communication device Download PDF

Info

Publication number
KR970068369A
KR970068369A KR1019960007726A KR19960007726A KR970068369A KR 970068369 A KR970068369 A KR 970068369A KR 1019960007726 A KR1019960007726 A KR 1019960007726A KR 19960007726 A KR19960007726 A KR 19960007726A KR 970068369 A KR970068369 A KR 970068369A
Authority
KR
South Korea
Prior art keywords
hdlc
data
transmission
memory
state information
Prior art date
Application number
KR1019960007726A
Other languages
Korean (ko)
Other versions
KR100207662B1 (en
Inventor
김준구
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960007726A priority Critical patent/KR100207662B1/en
Publication of KR970068369A publication Critical patent/KR970068369A/en
Application granted granted Critical
Publication of KR100207662B1 publication Critical patent/KR100207662B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/28—Flow control; Congestion control in relation to timing considerations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9005—Buffering arrangements using dynamic buffer space allocation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)

Abstract

본 발명은 하나의 HDLC 송수신기를 사용하여 복수의 채널에 대한 송수신 데이터를 처리하는 HDLC 통신장치에 관한 것으로서, 마이크로 제어기의 명령을 받아 수신된 데이터의 읽기 및 송신할 데이터의 쓰기 기능을 수행하는 마이크로제어기 인터페이스부; 송신할 데이터를 저장하는 송신용메모리; 수신된 데이터를 저장하고, 저장된 데이터가 출력되는 수신용메모리; 시간슬롯 전이구간에서 각 채널에 대응하는 HDLC 송수신기의 상태정보를 갱신하여 저장하는 상태정보저장부; 직렬데이터로 변환하고, HDLC 프레임 데이터를 생성하는 HDLC 송신기; 수신 HDLC 프레임 데이터에서 플래그를 제거하고 CRC검사를 하여 에러 검출을 하고 병렬데이터로 변환하는 HDLC 수신기; 해당 채널을 선택하여 HDLC 프레임 데이터를 출력하는 멀티플렉서; 및 해당 채널에 HDLC 프레임 데이터를 출력하는 디멀티플렉서를 포함함을 특징으로 한다.The present invention relates to an HDLC communication apparatus for processing transmission / reception data for a plurality of channels by using one HDLC transceiver, and more particularly to an HDLC communication apparatus for receiving data from a microcontroller for reading received data and writing data to be transmitted An interface unit; A transmission memory for storing data to be transmitted; A receiving memory for storing received data and outputting stored data; A state information storage unit for updating and storing state information of the HDLC transceiver corresponding to each channel in a time slot transition period; An HDLC transmitter for converting the serial data into serial data and generating HDLC frame data; An HDLC receiver for removing a flag from the received HDLC frame data and performing CRC check to detect an error and convert the error into parallel data; A multiplexer for selecting the corresponding channel and outputting HDLC frame data; And a demultiplexer for outputting HDLC frame data to the corresponding channel.

본 발명에 의하면 4개의 HDLC 송수신기에 분산되어 있는 송수신용 FIFO을 위한 램을 하나의 FIFO로 구현하므로써 리던던시를 줄이고 칩 크기를 줄일 수 있으며, 마이크로제어기와의 인터페이스를 단순화 한다.According to the present invention, the RAM for the transmission / reception FIFO distributed in the four HDLC transceivers is implemented as one FIFO, thereby reducing the redundancy, reducing the chip size, and simplifying the interface with the microcontroller.

Description

고수준 데이터 통신제어(HDLC) 통신 장치High-level data communication control (HDLC) communication device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 본 발명의 일실시예에 해당하는 하나의 고수준데이터 통시제어 (HDLC) 송수신기를 사용하여 4채널에 대한 송수신 데이터를 처리하는 HDLC 통신 장치의 구성을 도시한 구성도이다.FIG. 3 is a block diagram illustrating a configuration of an HDLC communication apparatus that processes transmission / reception data for four channels using one high-level data transmission control (HDLC) transceiver according to an embodiment of the present invention.

Claims (4)

하나의 고수준데이터통신제어(HDLC) 송수신기를 사용하여 복수의 채널에 대한 송수신 데이터를 처리하는 HDLC 통신장치에 있어서, 마이크로제어기의 명령을 받아 수신된 데이터의 읽기 및 송신할 데이터의 쓰기 기능을 수행하는 마이크로제어기 인터페이스부; 상기 마이크로제어기 인터페이스부에 의해 송신할 데이터를 저장하는 송신용 메모리; 수신된 데이터를 저장하고, 상기 마이크로제어기 인터페이스부에 의해 상기 저장된 데이터가 출력되는 수신용메모리; 시간슬롯 전이 구간에서 스와핑(swapping) 방식을 이용하여 각 채널에 대응하는 HDLC 송수신기의 상태정보를 갱신하여 저장하는 상태정보 저장부; 상기 상태정보 저장부의 해당 채널의 상태정보를 읽어 들여, 상기 송신용 메모리의 송신 데이터를 받아 직렬데이터로 변환하고, HDLC 프레임 데이터를 생성하는 HDLC 송신기; 상기 상태정보 저장부의 해당 채널의 상태 정보를 읽어 들여, 직렬로 된 수신 HDLC 프레임 데이터를 받아 플래그를 제거하고 CRC검사를 하여 에러 검출을 하고 병렬데이터로 변환하는 HDLC 수신기; HDLC 프레임 데이터를 수신하여 할당된 시간 슬롯에 대응하는 채널을 선택하여 상기 HDLC 수신기로 HDLC 프레임 데이터를 출력하는 멀티플렉서; 및 상기 HDLC 송신기에서 생성된 직렬로 된 HDLC 프레임 데이터를 할당된 시간 슬롯에 대응하는 처널에 상기 HDLC 프레임 데이터를 출력하는 디멀티플렉서를 포함함을 특징으로 하는 HDLC 통신장치.An HDLC communication apparatus for processing transmission / reception data for a plurality of channels using a high-level data communication control (HDLC) transceiver, the HDLC communication apparatus comprising: A microcontroller interface unit; A transmission memory for storing data to be transmitted by said microcontroller interface unit; A receiving memory for storing received data and outputting the stored data by the microcontroller interface unit; A state information storage unit for updating and storing state information of the HDLC transceiver corresponding to each channel using a swapping scheme in a time slot transition period; An HDLC transmitter for reading status information of a corresponding channel of the status information storage unit, receiving transmission data of the transmission memory, converting the transmission data into serial data, and generating HDLC frame data; An HDLC receiver that reads state information of a corresponding channel of the state information storage unit, receives serial HDLC frame data, removes a flag, performs CRC check to detect an error, and converts the error into parallel data; A multiplexer for receiving HDLC frame data and selecting a channel corresponding to the allocated time slot and outputting HDLC frame data to the HDLC receiver; And a demultiplexer for outputting the HDLC frame data generated in the HDLC transmitter to the corresponding channel corresponding to the allocated time slot. 제1항에 있어서, 상기 송신용 메모리 및 수신용 메모리는 선입선출 메모리임을 특징으로 하는 HDLC 통신장치.The HDLC communication apparatus according to claim 1, wherein the transmission memory and the reception memory are first-in-first-out memories. 제1항에 있어서, 상기 송신용 메모리 및 수신용 메모리는 채널수에 해당하는 메모리 영역을 구비하고, 상기 할당된 메모리 영역은 서로 독립적임을 특징으로 하는 HDLC 통신장치.The HDLC communication apparatus of claim 1, wherein the transmission memory and the reception memory have memory areas corresponding to the number of channels, and the allocated memory areas are independent from each other. 제1항에 있어서, 상기 상태정보 저장부의 상태정보는 시간슬롯에 해당하는 채널의 HDLC 프레임의 CRC 값; 및 송수신 시 HDLC 프레임 데이터에서 1개의 갯수를 카운트하는 카운트 값을 포함함을 특징으로 하는 HDLC 통신장치.The apparatus of claim 1, wherein the status information of the state information storage unit includes a CRC value of an HDLC frame of a channel corresponding to a time slot; And a count value counting one number of HDLC frame data at the time of transmission and reception. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960007726A 1996-03-21 1996-03-21 Hdlc communication apparatus KR100207662B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960007726A KR100207662B1 (en) 1996-03-21 1996-03-21 Hdlc communication apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960007726A KR100207662B1 (en) 1996-03-21 1996-03-21 Hdlc communication apparatus

Publications (2)

Publication Number Publication Date
KR970068369A true KR970068369A (en) 1997-10-13
KR100207662B1 KR100207662B1 (en) 1999-07-15

Family

ID=19453617

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960007726A KR100207662B1 (en) 1996-03-21 1996-03-21 Hdlc communication apparatus

Country Status (1)

Country Link
KR (1) KR100207662B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000046137A (en) * 1998-12-31 2000-07-25 김영환 Apparatus and method for removing packet error in hdlc router
KR100551158B1 (en) * 1998-12-31 2006-05-25 유티스타콤코리아 유한회사 HDLC communication device in base station of mobile communication system and communication method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020087511A (en) * 2001-05-11 2002-11-23 엘지이노텍 주식회사 A control device for serial data communication

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000046137A (en) * 1998-12-31 2000-07-25 김영환 Apparatus and method for removing packet error in hdlc router
KR100551158B1 (en) * 1998-12-31 2006-05-25 유티스타콤코리아 유한회사 HDLC communication device in base station of mobile communication system and communication method thereof

Also Published As

Publication number Publication date
KR100207662B1 (en) 1999-07-15

Similar Documents

Publication Publication Date Title
KR960006379A (en) Signal receiver
US6553424B1 (en) Circular buffer for a TDMA data transmission station and corresponding data transmission station
KR970068369A (en) High-level data communication control (HDLC) communication device
WO2003025740A3 (en) Serial communication device with dynamic filter allocation
KR970024724A (en) Serial data receiving and sending device
ES2070739A2 (en) Interface device for format conversion.
KR200220193Y1 (en) High Level Data Link Controls
KR0181485B1 (en) Data-buffering device for data telecommunication
KR100900958B1 (en) Apparatus and method for multiplexing channel data for supporting variable transmission rate
KR100680525B1 (en) Apparatus and method of transmitting data by using hdlc in a optical transmission system
EP0446335A4 (en) Packet/fast packet switch for voice and data
KR950022491A (en) Packet Data Exchange Processing Method of Digital Mobile Communication Control Station
KR920001548B1 (en) Apparatus and method transmitting/receiving data through channels to have clear channel capability
KR970071294A (en) A direct memory access (DMA) device using a serial communication controller (SCC)
KR200170149Y1 (en) Apparatus for transmitting and receiving data by single cpu
KR100430652B1 (en) Transmission Speed Translating Equipment
KR920007488B1 (en) Universial signal transceiving circuit
JPH06284140A (en) Local communication system
JPS6394730A (en) Split multiplex packet signal decoding device
JP3420466B2 (en) TDMA radio
JPH0514455B2 (en)
KR100246556B1 (en) Address filter of synchronous router of personal communication system base station
JP3098372B2 (en) Communication device
KR920013146A (en) Fieldbus Interface Board
KR970049622A (en) Mass memory data transmission device and method

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080328

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee