KR970066849A - Hardware device that helps bit operation in programmable controller - Google Patents

Hardware device that helps bit operation in programmable controller Download PDF

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Publication number
KR970066849A
KR970066849A KR1019960009264A KR19960009264A KR970066849A KR 970066849 A KR970066849 A KR 970066849A KR 1019960009264 A KR1019960009264 A KR 1019960009264A KR 19960009264 A KR19960009264 A KR 19960009264A KR 970066849 A KR970066849 A KR 970066849A
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KR
South Korea
Prior art keywords
bit
microprocessor
data
hardware device
programmable controller
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Application number
KR1019960009264A
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Korean (ko)
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KR0174655B1 (en
Inventor
송승환
윤동화
이희영
장래혁
Original Assignee
이재운
포스코신기술연구조합
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Priority to KR1019960009264A priority Critical patent/KR0174655B1/en
Publication of KR970066849A publication Critical patent/KR970066849A/en
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Publication of KR0174655B1 publication Critical patent/KR0174655B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Programmable Controllers (AREA)

Abstract

본 발명은 프로그램형 제어기의 하드웨어 장치에 관한 것으로서, m개의 트라이스테이트버퍼로 이루어진 제1,2버퍼부(1),(2)와 m개의 멀티플렉서로 이루어진 제1~3멀티플렉서부(3), (4), (5), 멀티플렉서부(6), 래치부(7) 및 디코더(8)로 구성되어 비트 명령 수행시 한 명령당 1~2회의 쉬프트 작업을 없앨 수 있으므로 비트 명령 수행시 수행시간이 최소 20%에서 최대 50%까지 감소되는 효과가 있는 프로그램형 제어기에서 비트연산을 도와주는 하드웨어 장치이다.The present invention relates to a hardware device of a programmable controller, which comprises first and second buffer units (1) and (2) consisting of m tri-state buffers and first to third multiplexer units (3) 4, and 5, the multiplexer 6, the latch 7, and the decoder 8, it is possible to eliminate one or two shift operations per instruction when a bit instruction is executed. It is a hardware device that helps bit operation in a programmable controller with a reduction of at least 20% to 50%.

Description

프로그램형 제어기에서 비트연산을 도와주는 하드웨어 장치Hardware device that helps bit operation in programmable controller

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 본 발명 프로그램형 제어기에서 비트연산을 도와주는 하드웨어 장치의 구성도, 제4도는 본 발명 하드웨어장치를 채용한 프로그램형 제어기의 구성도.FIG. 3 is a block diagram of a hardware device that assists bit operations in the programmable controller of the present invention; FIG. 4 is a block diagram of a programmable controller employing the hardware device of the present invention;

Claims (1)

m개의 트라이스테이트버퍼로 이루어진 제1,2버퍼부(1), (2)와 m개의 멀티플렉서로 이루어진 제1~3멀티플렉서부(3), (4), (5), 멀티플렉서부(6), 래치부(7) 및 디코더(8)로 구성되어 마이크로프로세서(11)가 메모리(12)를 억세스할 때 데이타가 비트 데이터인지 워드데이터인지는 어드레스로 구별하고, 메모리리드 싸이클에서 비트선택어드레스신호를 입력받아 비트선택 어드레스신호가 워드선택신호인 경우 메모리(12)에서 출력되는 데이터 값을 그대로 마이크로프로세서(11)로 전달하고 비트선택어드레스신호가 비트선택신호인 경우는 메모리(12)에서 출력되는 데이터를 지정된 필드에 있는 비트만을 선택하여 마이크로프로세서(11)의 특정 비트로 출력하며, 메모리라이트 싸이클에서는 입력된 비트선택어드레서신호가 워드선택신호인 경우 마이크로프로세서(11)에서 출력되는 데이터 값을 그대로 메모리(12)에 전달하고 비트선택어드레스신호가 비트선택신호인 경우 마이크로프로세서(11)에서 출력되는 데이터중 특정 비트만을 지정된 필드에 출력하는 것을 특징으로 하는 프로그램형 제어기에서 비트연산을 도와주는 하드웨어 장치.The first to third multiplexer units 3, 4, and 5, the multiplexer unit 6, and the first to third multiplexer units including m first and second tristate buffers 1 and 2 and m multiplexers, A latch unit 7 and a decoder 8 to discriminate whether the data is bit data or word data when the microprocessor 11 accesses the memory 12 by an address, When the bit selection address signal is a word selection signal, the data value output from the memory 12 is directly transmitted to the microprocessor 11. When the bit selection address signal is a bit selection signal, the data output from the memory 12 The microprocessor 11 selects only the bit in the designated field and outputs it as a specific bit of the microprocessor 11. In the memory write cycle, when the input bit selection address signal is a word selection signal, And outputs only a specific bit of data output from the microprocessor 11 to a designated field when the bit selection address signal is a bit selection signal. A hardware device that assists bit operations. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960009264A 1996-03-29 1996-03-29 Hardware device that helps bit operations in programmable controllers KR0174655B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960009264A KR0174655B1 (en) 1996-03-29 1996-03-29 Hardware device that helps bit operations in programmable controllers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960009264A KR0174655B1 (en) 1996-03-29 1996-03-29 Hardware device that helps bit operations in programmable controllers

Publications (2)

Publication Number Publication Date
KR970066849A true KR970066849A (en) 1997-10-13
KR0174655B1 KR0174655B1 (en) 1999-04-01

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