KR970063712A - Method of manufacturing semiconductor device with insulating film of ONO structure - Google Patents

Method of manufacturing semiconductor device with insulating film of ONO structure Download PDF

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Publication number
KR970063712A
KR970063712A KR1019960002787A KR19960002787A KR970063712A KR 970063712 A KR970063712 A KR 970063712A KR 1019960002787 A KR1019960002787 A KR 1019960002787A KR 19960002787 A KR19960002787 A KR 19960002787A KR 970063712 A KR970063712 A KR 970063712A
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KR
South Korea
Prior art keywords
gas
semiconductor device
temperature
atmosphere
ramp
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KR1019960002787A
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Korean (ko)
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KR0183820B1 (en
Inventor
김종한
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김광호
삼성전자 주식회사
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Priority to KR1019960002787A priority Critical patent/KR0183820B1/en
Publication of KR970063712A publication Critical patent/KR970063712A/en
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Publication of KR0183820B1 publication Critical patent/KR0183820B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 ONO 구조의 절연막을 갖춘 반도체 장치의 제조 방법에 관한 것으로서, 본 발명에 따른 반도체 장치의 제조 방법에 따르면 절연막을 형성하기 위하여 600∼800℃의 초기 온도로 유지되는 반응로를 N2가스를 함유하는 분위기로하여 온도를 850∼1000℃로 점차 상승시키는 램프-업(ramp-up) 단계와, 상기 반응로를 순수한 N2O 가스를 함유하는 분위기로 하여 상기 도전층을 소정의 두께로 산화시키는 산화 단계와, 상기 산혼단계에서의 온도를 유지하면서 N2가스 분위기에서 어닐링하는 어닐링 단계와, 상기 반응로의 온도를 다시 초기 온도로 점차 하강시키는 램프-다운(ramp-down) 단계를 포함한다. 본 발명에 의하면, 별도의 공정을 추가하지 않고도 반도체 장치의 고집적화에 따라 층간 절연막의 특성이 저하되는 것을 감소시킬수 있고, 따라서 반도체 장치의 신뢰도를 향상시킬 수 있다.According to the method for manufacturing a semiconductor device according to the present invention, a reaction furnace maintained at an initial temperature of 600 to 800 ° C. is formed in an N 2 gas and in an atmosphere containing lamp to rise gradually to a temperature of 850~1000 ℃ the - to an atmosphere containing up (ramp-up) phase and, N 2 O gas as the pure reaction the conductive layer to a desired thickness And an annealing step of annealing in an N 2 gas atmosphere while maintaining the temperature in the above-mentioned acid step, and a ramp-down step of gradually lowering the temperature of the reactor to an initial temperature do. According to the present invention, it is possible to reduce the deterioration of the characteristics of the interlayer insulating film due to the high integration of the semiconductor device without adding a separate step, thereby improving the reliability of the semiconductor device.

Description

ONO 구조의 절연막을 갖춘 반도체 장치의 제조 방법Method of manufacturing semiconductor device with insulating film of ONO structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제8도는 본 발명에 따라 제조되는 ONO 구조의 중간 절연막에서 하부의 산화막을 형성하는 온도 사이클을 도시한 것이다.FIG. 8 illustrates a temperature cycle for forming an oxide film on a lower surface of an intermediate insulating film of an ONO structure manufactured according to the present invention.

제9도는 본 발명에 따라 제조된 ONO 구조의 중간 절연막이 도전층 사이에 적층된 상태를 도시한 도면이다.FIG. 9 is a diagram showing a state in which an intermediate insulating film of an ONO structure manufactured according to the present invention is laminated between conductive layers. FIG.

Claims (3)

폴리실리콘으로 구성되는 도전층 위에 적층된 ONO(Oxde/Nitride/Oxide) 구조의 절연막을 포함하는 반도체 장치의 제조 방법에 있어서, 상기 졀연막을 형성하는 단계는 600∼800℃의 초기 온도로 유지되는 반응로를 N2가스를 함유하는 분위기로 하여 온도를 850∼1000℃로 점차 상승시키는 램프-업(ramp-up)단계와, 상기 반응로를 순수한 N20 가스를 함유되는 분위기로 하여 상기 도전층을 소정의 두께로 산화시키는 산화 단계와, 상기 산화 단계에서의 온도를 유지하면서 N2가스 분위기에서 어닐링하는 어닐링 단계와, 상기 반응로의 온도를 다시 초기 온도로 점차 하강시키는 램프-다운(ramp-down) 단계를 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.A method of manufacturing a semiconductor device including an insulating film of ONO (Oxde / Nitride / Oxide) structure stacked on a conductive layer made of polysilicon, wherein the step of forming the insulating film is maintained at an initial temperature of 600 to 800 ° C to the reactor gradually rises to a temperature of 850~1000 ℃ to an atmosphere containing a N 2 gas ramp-up (ramp-up) step and said conductive to the atmosphere in the reactor is contained the pure N 2 0 gas An annealing step of annealing the layer in a N 2 gas atmosphere while maintaining the temperature in the oxidation step; and a ramp-down (ramp-down) step of gradually lowering the temperature of the reactor to the initial temperature, -depositing the semiconductor device. 제1항에 있어서, 상기 램프-업 단계에서 N2가스를 함유하는 반응로의 분위기는 1∼10%의 O2+잔량의 N2가스 분위기, 또는 1∼100%의 N2O+잔량의 N2가스 분위기인 것을 특징으로 하는 반도체 장치의 제조 방법.The method of claim 1, wherein the lamp-atmosphere of the reactor containing a N 2 gas from the step-up of 1 to 10% of O 2 + residual amount of the N 2 gas atmosphere, or a remaining amount of 1~100% N 2 O + N 2 < / RTI > gas atmosphere. 제1항에 있어서, 상기 산화 단계에서 N2O 가스를 함유하는 분위기는 0∼100%의 N2O 가스+잔량의 O2가스 분위기인 것을 특징으로 하는 반도체 장치의 제조 방법.The manufacturing method of a semiconductor device according to claim 1, wherein the atmosphere containing N 2 O gas in the oxidation step is an O 2 gas atmosphere of 0 to 100% N 2 O gas + remaining amount. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960002787A 1996-02-06 1996-02-06 Method of manufacturing semiconductor device having ono structure insulating film KR0183820B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960002787A KR0183820B1 (en) 1996-02-06 1996-02-06 Method of manufacturing semiconductor device having ono structure insulating film

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Application Number Priority Date Filing Date Title
KR1019960002787A KR0183820B1 (en) 1996-02-06 1996-02-06 Method of manufacturing semiconductor device having ono structure insulating film

Publications (2)

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KR970063712A true KR970063712A (en) 1997-09-12
KR0183820B1 KR0183820B1 (en) 1999-03-20

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100318683B1 (en) * 1998-12-17 2001-12-28 윤종용 Method of forming oxide/nitride/oxide dielectric layer
KR100333180B1 (en) * 1998-06-30 2003-06-19 주식회사 현대 디스플레이 테크놀로지 TFT-LCD Manufacturing Method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100333180B1 (en) * 1998-06-30 2003-06-19 주식회사 현대 디스플레이 테크놀로지 TFT-LCD Manufacturing Method
KR100318683B1 (en) * 1998-12-17 2001-12-28 윤종용 Method of forming oxide/nitride/oxide dielectric layer

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