KR970060770A - Timing recovery system of digital data - Google Patents

Timing recovery system of digital data Download PDF

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Publication number
KR970060770A
KR970060770A KR1019960000670A KR19960000670A KR970060770A KR 970060770 A KR970060770 A KR 970060770A KR 1019960000670 A KR1019960000670 A KR 1019960000670A KR 19960000670 A KR19960000670 A KR 19960000670A KR 970060770 A KR970060770 A KR 970060770A
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KR
South Korea
Prior art keywords
digital data
offset
recovery system
timing
converter
Prior art date
Application number
KR1019960000670A
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Korean (ko)
Other versions
KR100209647B1 (en
Inventor
최형진
이경하
김용훈
Original Assignee
구자홍
엘지전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 구자홍, 엘지전자 주식회사 filed Critical 구자홍
Priority to KR1019960000670A priority Critical patent/KR100209647B1/en
Publication of KR970060770A publication Critical patent/KR970060770A/en
Application granted granted Critical
Publication of KR100209647B1 publication Critical patent/KR100209647B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

본 발명은 디지탈 데이터 수신시스템에 관한 것으로서, 특히 기저대역(Baseband)에서 동작되도록 하여 타이밍 동기를 빠르게 복원하는 디지탈 데이터의 타이밍 복원시스템에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data receiving system, and more particularly, to a digital data timing recovery system for quickly recovering timing synchronization by operating in a baseband.

상기와 같은 목적을 달성하기 위한 본 발명에 따른 디지탈 데이터의 타이밍 복원시스템은 기저대역신호를 입력클럭에 따라서 샘플링하는 A/D 컨버터와, 상기 A/D 컨버터의 샘플링 출력중 타이밍 동기에러를 추출하는 타이밍 동기 에러추출부와, 상기 타이밍 동기에러의 오프셋을 보상하는 오프셋 보상부와, 오프셋 보상된 타이밍 에러신호를 필터링하고 그 출력전압으로 발진 주파수를 발생시켜 A/D 컨버터의 샘플링 클럭을 구동하는 에러보상부로 이루어짐을 특징으로 한다. 따라서, 본 발명에 따른 디지탈 데이터의 타이밍 복원시스템은 통과대역을 기저대역으로 변환시켜 시스템을 간략화하므로 제작비용을 줄일 수 있으며, 제4도에 나타낸 특성비교 그래프와 같이 오프셋을 보상하면 데이터 패턴에 따른 수렵지점의 변화가 현저하게 감소함은 물론 정상상태 지터량이 저하되므로 복원성능이 향상되는 효과가 있다.According to an aspect of the present invention, there is provided a digital data timing recovery system including an A / D converter for sampling a baseband signal according to an input clock, An offset compensator for compensating for the offset of the timing synchronization error, an error compensator for filtering the offset compensated timing error signal and generating an oscillation frequency at an output voltage thereof to drive a sampling clock of the A / D converter, And a compensation unit. Accordingly, the timing recovery system of digital data according to the present invention can reduce the manufacturing cost by simplifying the system by converting the pass band to the base band. If the offset is compensated as shown in the characteristic comparison graph shown in FIG. 4, The change of the hunting point is remarkably reduced and the amount of the normal state jitter is reduced, so that the restoration performance is improved.

Description

디지탈 데이터의 타이밍 복원시스템Timing recovery system of digital data

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 본 발명에 따른 디지탈 데이터의 타이밍 복원시스템의 구성도.FIG. 3 is a block diagram of a timing recovery system for digital data according to the present invention; FIG.

Claims (2)

기저대역신호를 입력클럭에 따라서 샘플링하는 A/D 컨버터와, 상기 A/D 컨버터의 샘플링 출력중 타이밍 동기에러를 추출하는 타이밍 동기 에러추출부와, 상기 타이밍 동기에러의 오프셋을 보상하는 오프셋 보상부와, 오프셋 보상된 타이밍 에러신호를 필터링하고 그 출력전압으로 발진주파수를 발생시켜 A/D 컨버터의 샘플링 클럭을 구동하는 에러보상부로 이루어짐을 특징으로 하는 디지탈 데이터의 타이밍 복원시스템.An A / D converter for sampling a baseband signal according to an input clock; a timing synchronization error extracting unit for extracting a timing synchronization error during a sampling output of the A / D converter; And an error compensator for filtering the offset compensated timing error signal and generating an oscillation frequency based on the output voltage to drive a sampling clock of the A / D converter. 제 1 항에 있어서, 상기 타이밍 동기에서 추출부와 성능은 필터대역폭에 의해 결정됨을 특징으로 하는 디지탈 데이터의 타이밍 복원시스템.The system according to claim 1, wherein the timing synchronization unit and the performance unit are determined by a filter bandwidth. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960000670A 1996-01-15 1996-01-15 Timing recovery system of digital data KR100209647B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960000670A KR100209647B1 (en) 1996-01-15 1996-01-15 Timing recovery system of digital data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960000670A KR100209647B1 (en) 1996-01-15 1996-01-15 Timing recovery system of digital data

Publications (2)

Publication Number Publication Date
KR970060770A true KR970060770A (en) 1997-08-12
KR100209647B1 KR100209647B1 (en) 1999-07-15

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Application Number Title Priority Date Filing Date
KR1019960000670A KR100209647B1 (en) 1996-01-15 1996-01-15 Timing recovery system of digital data

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100316026B1 (en) * 1999-06-30 2001-12-20 박종섭 Device for recovering and discriminating symbol timing error in data transmission of multi-level
KR100474995B1 (en) * 1997-08-21 2005-06-07 삼성전자주식회사 ADC clock timing error recovery circuit and recovery method in the signal preprocessing area of the PR4 signal processing channel

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474995B1 (en) * 1997-08-21 2005-06-07 삼성전자주식회사 ADC clock timing error recovery circuit and recovery method in the signal preprocessing area of the PR4 signal processing channel
KR100316026B1 (en) * 1999-06-30 2001-12-20 박종섭 Device for recovering and discriminating symbol timing error in data transmission of multi-level

Also Published As

Publication number Publication date
KR100209647B1 (en) 1999-07-15

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