KR970057931A

KR970057931A - Program reference clock reproducing device of system decoder

Info

Publication number: KR970057931A
Application number: KR1019950061365A
Authority: KR
Inventors: 김종일
Original assignee: 배순훈; 대우전자 주식회사
Priority date: 1995-12-28
Filing date: 1995-12-28
Publication date: 1997-07-31

Abstract

본 발명은 시스템 복호화기의 프로그램 기준 클럭 재생장치에 관한 것으로, 초기 PCR_ext 데이타를 입력받아 로딩하고, 로딩된 값부터 시스템 클럭을 카운팅하여 카운트 값을 출력하는 제1카운터(20)와; 상기 제1카운터(20)에서 출력된 카운트 값을 299와 비교하여 상기 카운트 값이 299이면 캐리를 출력하는 비교기(22); 초기 PCR_base 데이타를 입력받아 로딩하고, 로딩된 값부터 상기 비교기(22)에서 출력된 캐리를 카운팅하여 카운트 값을 출력하는 제2카운터(24) 및 매 시스템 클럭 마다 시스템 클럭에 동기시켜 상기 제1카운터(20)에서 출력된 카운트 값과 상기 제2카운터(24)에서 출력된 카운트 값을 조합하여 로딩하는 조합부(26)를 포함하여 구성되어, 프로그램 기준 클럭데이타를 재생할 수 있는 것이다.The present invention relates to a program reference clock reproducing apparatus of a system decoder, comprising: a first counter (20) for receiving and loading initial PCR_ext data, counting a system clock from the loaded value, and outputting a count value; A comparator 22 for comparing a count value output from the first counter 20 with 299 and outputting a carry when the count value is 299; A second counter 24 which counts the carry output from the comparator 22 and outputs a count value from the loaded value and the first counter in synchronization with the system clock at every system clock And a combination unit 26 which loads the count value output from 20 and the count value output from the second counter 24 in combination, thereby reproducing the program reference clock data.

Description

Program reference clock reproducing device of system decoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 MPEG2 시스템 부호화기의 개략적인 블럭도,1 is a schematic block diagram of an MPEG2 system encoder;

제2도는 패킷 데이타의 구조도,2 is a structural diagram of packet data;

제3도는 본 발명에 따른 시스템 복호화기의 프로그램 기준 클럭 재생장치의 블럭도.3 is a block diagram of a program reference clock reproducing apparatus of a system decoder according to the present invention.

Claims

An apparatus for reproducing a program reference clock, comprising: a first counter (20) for receiving and loading initial PCR_ext data, counting a system clock from the loaded value, and outputting a count value; A comparator 22 for comparing a count value output from the first counter 20 with 299 and outputting a carry when the count value is 299; A second counter 24 which counts the carry output from the comparator 22 and outputs a count value from the loaded value and the first counter in synchronization with the system clock at every system clock And a combiner (26) which combines and loads the count value output from (20) and the count value output from the second counter (24).

The counter of claim 1, wherein the first counter 20 is a 9-bit counter of the modular 300 that is set to 0 again at the next clock and repeatedly counts every 300 cycles to output the count value when the count value reaches 299. A program reference clock reproducing apparatus of a system decoder.

The apparatus of claim 1, wherein the second counter (24) is a 33-bit counter.

The apparatus of claim 1, wherein the initial PCR_ext data and the initial PCR_base data are PCR data first received when the system decoder is initially driven.

The apparatus of claim 1, wherein the combining unit (26) outputs the loaded PCR data when a PCR request signal is input from the outside.

※ Note: The disclosure is based on the initial application.