KR970057057A - Phase-locked loop for frequency hopping communication system - Google Patents

Phase-locked loop for frequency hopping communication system Download PDF

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KR970057057A
KR970057057A KR1019950056544A KR19950056544A KR970057057A KR 970057057 A KR970057057 A KR 970057057A KR 1019950056544 A KR1019950056544 A KR 1019950056544A KR 19950056544 A KR19950056544 A KR 19950056544A KR 970057057 A KR970057057 A KR 970057057A
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control voltage
digital
phase
voltage
control
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KR1019950056544A
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KR100206462B1 (en
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박재선
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김광호
삼성전자 주식회사
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Priority to KR1019950056544A priority Critical patent/KR100206462B1/en
Priority to CN96117916A priority patent/CN1064197C/en
Priority to US08/825,934 priority patent/US5926515A/en
Publication of KR970057057A publication Critical patent/KR970057057A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
    • H03L7/189—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop comprising a D/A converter for generating a coarse tuning voltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

1.청구범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs

위상동기루프에 관한 것이다.It relates to a phase locked loop.

2.발명이 해결하려고 하는 기술적 과제2. Technical problem that the invention tries to solve

주파수도약방식의 통신시스템에 보다 적합하게 이용될 수 있는 위상동기루프를 구현한다.It implements a phase-locked loop that can be used more suitably in a frequency hopping communication system.

3.발명의 해결방법의 요지3. Summary of the solution of the invention

주파수도약방식의 통신시스템에서 송신과 수신동작이 수행되지 않는 시간동안에 사용되어질 주파수에 대한 제어전압을 주기적으로 평가하여 기억장소에 저장하여 두었다가 송신 및 수신동작이 실제 수행될 시 이미 저장되어 있는 제어전압값을 전압제어발진기에 제공함으로써 전압제어발진기의 부품편차 및 주위환경의 변화에 의한 주파수편차로 길어지는 동기시간을 개선하는 위상동기루프를 제공한다.In the frequency hopping communication system, the control voltage for the frequency to be used during the time when the transmission and reception operations are not performed is periodically evaluated and stored in a storage location, and the control voltage already stored when the transmission and reception operations are actually performed. By providing the value to the voltage controlled oscillator, a phase locked loop is provided which improves the synchronous time lengthened by the component deviation of the voltage controlled oscillator and the frequency deviation caused by the change of the surrounding environment.

Description

주파수도약방식의 통신시스템을 위한 위상동기루프Phase-locked loop for frequency hopping communication system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 종래기술에 따른 위상동기루프의 구성을 보여주는 도면.2 is a view showing the configuration of a phase locked loop according to the prior art.

Claims (7)

주파수도약방식의 통신시스템을 위한 위상동기루프에 있어서, 일련의 제어전압을 디지탈적으로 저장하고 있는 버퍼와, 인가되는 디지탈의 제어전압을 아날로그의 제어전압으로 변환하는 디지탈/아날로그변환기와, 상기 디지탈/아날로그변환기로부터 출력되는 아날로그의 제어전압에 의존하는 주파수를 발진하는 전압제어발진기와, 상기 전압제어발진기의 출력을 가변분주비에 따라 분주하는 가변분주기와, 상기 가변분주기로부터 출력되는 신호의 위상과 기준신호의 위상을 비교하고 그 비교결과를 나타내는 위상차신호를 출력하는 위상비교기와, 상기 위상차신호를 저역통과필터링하는 저역통과필터와, 상기 저역통과필터로부터 출력되는 아날로그신호의 레벨을 기준레벨과 비교하고 그 비교결과를 디지탈신호로 출력하는 레벨검출기와, 송수신동작이 수행되지 않는 동안에는 상기 디지탈신호가 미리 설정된 범위이내의 값일 때까지 상기 버퍼에 저장되어 있는 일련의 제어전압을 변화시키면서 리드하여 상기 디지탈/아날로그변환기로 제공함으로써 도약을 위한 사용주파수에 관련하는 제어전압을 선택하여 저장하고, 송수신동작중에는 도약을 위한 사용주파수에 관련하여 저장되어 있는 제어전압을 상기 디지탈/아날로그변환기로 제공하는 제어수단으로 구성함을 특징으로 하는 위상동기루프.A phase locked loop for a frequency hopping communication system, comprising: a buffer for storing a series of control voltages digitally, a digital / analog converter for converting an applied digital control voltage into an analog control voltage, and the digital signal. A voltage controlled oscillator for oscillating a frequency depending on an analog control voltage output from an analog converter, a variable divider for dividing an output of the voltage controlled oscillator according to a variable division ratio, and a signal output from the variable divider. A phase comparator for comparing the phase of the phase and the reference signal and outputting a phase difference signal indicating the comparison result, a low pass filter for low pass filtering the phase difference signal, and a level of an analog signal output from the low pass filter; Level detector for comparing and comparing the result with a digital signal and outputting the result as a digital signal. While the operation is not performed, the digital signal is read while varying a series of control voltages stored in the buffer until the digital signal is within a preset range, and provided to the digital / analog converter to control the frequency related to the use frequency for the jump. And a control means for selecting and storing the voltage and providing the control voltage stored in relation to the frequency used for the hopping operation to the digital / analog converter during the transceiving operation. 제1항에 있어서, 상기 제어수단은 상기 레벨검출기로부터 출력되는 디지탈신호의 레벨이 상기 설정범위의값보다 작은 경우에는 상기 버퍼에 저장되어 있는 제어전압의 값을 증가시키면서 리드동작을 수행하고, 상기 레벨검출기로부터 출력되는 디지탈신호의 레벨이 상기 설정범위의 값보다 큰 경우에는 상기 버퍼에 저장되어 있는 제어전압의 값을 감소시키면서 리드동작을 수행하는 것을 특징으로 하는 위상동기루프.The method of claim 1, wherein the control means performs a read operation while increasing the value of the control voltage stored in the buffer when the level of the digital signal output from the level detector is smaller than the value of the setting range. And a read operation is performed while reducing the value of the control voltage stored in the buffer when the level of the digital signal output from the level detector is greater than the value of the setting range. 주파수도약방식의 통신시스템을 위한 위상동기루프에 있어서, 일련의 제어전압을 디지탈적으로 저장하고 있는 제1버퍼와, 상기 제1버퍼에 연결되는 제2버퍼와, 인가되는 디지탈의 제어전압을 아날로그의 제어전압으로 변환하는 디지탈/아날로그변환기와, 상기 디지탈/아날로그변환기의 출력과 소정의 오프셋전압을 가산하는 가산기와, 상기 가산기로부터 출력되는 아날로그의 제어전압에 의존하는 주파수를 발진하는 전압제어발진기와, 상기 전압제어발진기의 출력을 가변분주비에 따라 분주하는 가변분주기와, 상기 가변분주기로부터 출력되는 신호의 위상과 기준신호의 위상을 비교하고 그 비교결과를 나타내는 위상차신호를 출력하는 위상비교기와, 상기 위상차신호를 저역통과필터링하는 저역통과필터와, 상기 저역통과필터로부터 출력되는 아날로그신호의 레벨을 기준레벨과 비교하고 그 비교결과를 디지탈신호로 출력하는 레벨검출기와, 송수신동작이 수행되지 않는 동안에는 상기 제1버퍼에 저장되어 있는 일련의 제어전압을 변화시키면서 리드하여 상기 디지탈/아날로그변환기로 제공하다가 상기 디지탈신호가 상기 설정범위이내의 값인경우 해당하는 제어전압을 도약을 위한 사용주파수에 관련시켜 상기 제2버퍼에 저장하고, 송수신동작중에는 상기 제2버퍼에 저장되어 있는 제어전압을 상기 디지탈/아날로그변환기로 제공하는 제어수단으로 구성함을 특징으로 하는 위상동기루프.A phase locked loop for a frequency hopping communication system, comprising: a first buffer that stores a series of control voltages digitally, a second buffer connected to the first buffer, and an applied digital control voltage. A digital / analog converter for converting the control voltage to a control voltage, an adder for adding the output of the digital / analog converter and a predetermined offset voltage, a voltage controlled oscillator for oscillating a frequency depending on the analog control voltage output from the adder; And a phase divider for dividing an output of the voltage controlled oscillator according to a variable division ratio, and comparing a phase of a signal output from the variable divider and a phase of a reference signal and outputting a phase difference signal representing the comparison result. A low pass filter for low pass filtering the phase difference signal, the low pass filter being output from the low pass filter A level detector for comparing the level of the analog signal with a reference level and outputting the result of the comparison as a digital signal; and reading and changing the series of control voltages stored in the first buffer while the transmission / reception operation is not performed. If the digital signal is within the setting range, the control signal is stored in the second buffer in relation to the frequency used for the leap, and the control is stored in the second buffer during the transmission / reception operation. And a control means for providing a voltage to the digital / analog converter. 제3항에 있어서, 상기 제어수단은 상기 레벨검출기로부터 출력되는 디지탈신호의 레벨이 상기 설정범위의 값보다 작은 경우에는 상기 버퍼에 저장되어 있는 제어전압의 값을 증가시키면서 리드동작을 수행하고, 상기 레벨검출기로부터 출력되는 디지탈신호의 레벨이 상기 설정범위의 값보다 큰 경우에는 상기 버퍼에 저장되어 있는 제어전압의 값을 감소시키면서 리드동작을 수행하는 것을 특징으로 하는 위상동기루프.The method of claim 3, wherein the control means performs a read operation while increasing the value of the control voltage stored in the buffer when the level of the digital signal output from the level detector is smaller than the value of the set range, And a read operation is performed while reducing the value of the control voltage stored in the buffer when the level of the digital signal output from the level detector is greater than the value of the setting range. 주파수도약방식의 통신시스템을 위한 위상동기루프에 있어서, 인가되는 디지탈의 제어전압을 아날로그의 제어전압으로 변환하는 디지탈/아날로그변환기와, 상기 디지탈/아날로그변환기로부터 출력되는 아날로그의 제어전압에 의존하는 주파수를 발진하는 전압제어발진기와, 상기 전압제어발진기의 출력을 가변분주비에 따라 분주하는 가변분주기와, 상기 가변분주기로부터 출력되는 신호의 위상과 기준신호의 위상을 비교하고 그 비교결과를 나타내는 위상차신호를 출력하는 위상비교기와, 상기 위상차신호를 저역통과필터링하는 저역통과필터와, 상기 저역통과필터로부터 출력되는 아날로그신호의 레벨을 기준레벨과 비교하고 그 비교결과를 디지탈신호로 출력하는 레벨검출기와, 송수신동작이 수행되지 않는 동안에는 일련의 제어전압을 변화시키면서 상기 디지탈/아날로그변환기로 제공하다가 상기 디지탈신호가 상기 설정범위이내의 값인 경우 해당하는 제어전압을 도약에 사용될 주파수를 위한 제어전압으로 평가하는 제어전압 평가수단과, 송수신동작중에는 상기 사용주파수를 위한 제어전압으로 평가된 제어전압을 상기 디지탈/아날로그변환기로 제공하는 제어전압 제공수단으로 구성함을 특징으로 하는 위상동기루프.In a phase-locked loop for a frequency hopping communication system, a digital / analog converter for converting an applied digital control voltage into an analog control voltage and a frequency dependent on an analog control voltage output from the digital / analog converter. A voltage controlled oscillator for oscillating the oscillator, a variable divider for dividing the output of the voltage controlled oscillator according to a variable division ratio, a phase of a signal output from the variable divider and a phase of a reference signal, and indicating a comparison result A phase comparator for outputting a phase difference signal, a low pass filter for low pass filtering the phase difference signal, a level detector for comparing the level of the analog signal output from the low pass filter with a reference level and outputting the comparison result as a digital signal And a series of control voltages are changed while the transmission / reception operation is not performed. Control voltage evaluating means for providing the digital / analog converter and evaluating a corresponding control voltage as a control voltage for a frequency to be used for hopping when the digital signal is within the set range; And a control voltage providing means for providing a control voltage evaluated as a control voltage to the digital / analog converter. 제5항에 있어서, 상기 제어전압 평가수단은 상기 레벨검출기로부터 출력되는 디지탈신호의 레벨이 상기설정범위의 값보다 작은 경우에는 해당하는 제어전압의 값을 증가시키면서 도약에 사용될 주파수를 위한 제어전압을 평가하고, 상기 레벨검출기로부터 출력되는 디지탈신호의 레벨이 상기 설정범위의 값보다 큰 경우에는 해당하는 제어전압의 값을 감소시키면서 도약에 사용될 주파수를 위한 제어전압을 평가하는 것을 특징으로 하는 위상동기루프.6. The control voltage evaluating means according to claim 5, wherein the control voltage evaluating means increases the control voltage for the frequency to be used for the jump while increasing the value of the corresponding control voltage when the level of the digital signal output from the level detector is smaller than the value of the setting range. And when the level of the digital signal output from the level detector is greater than the value of the setting range, evaluating the control voltage for the frequency to be used for the hopping while reducing the value of the corresponding control voltage. . 제5항에 있어서, 상기 디지탈/아날로그변환기와 상기 전압제어발진기의 사이에 접속되며, 상기 디지탈/아날로그변환기의 출력과 소정의 오프셋전압을 가산하여 상기 전압제어발진기로 제공하는 가산기를 더 포함함을 특징으로 하는 위상동기루프.6. The apparatus of claim 5, further comprising an adder connected between the digital / analog converter and the voltage controlled oscillator and adding the output of the digital / analog converter and a predetermined offset voltage to the voltage controlled oscillator. Characterized in phase synchronization loop. ※참고사항:최초출원 내용에 의하여 공개하는 것임.※ Note: This is to be disclosed based on the first application.
KR1019950056544A 1995-12-26 1995-12-26 Phase locked loop for frequency hopping communication KR100206462B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950056544A KR100206462B1 (en) 1995-12-26 1995-12-26 Phase locked loop for frequency hopping communication
CN96117916A CN1064197C (en) 1995-12-26 1996-12-24 Phase locked loop for communication system of frequency hopping type
US08/825,934 US5926515A (en) 1995-12-26 1997-04-01 Phase locked loop for improving a phase locking time

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CN103138753B (en) * 2011-11-23 2016-08-10 联想(北京)有限公司 Adjusting means, phaselocked loop, electronic equipment, bandwidth adjusting method and device

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