CN1064197C - Phase locked loop for communication system of frequency hopping type - Google Patents
Phase locked loop for communication system of frequency hopping type Download PDFInfo
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- CN1064197C CN1064197C CN96117916A CN96117916A CN1064197C CN 1064197 C CN1064197 C CN 1064197C CN 96117916 A CN96117916 A CN 96117916A CN 96117916 A CN96117916 A CN 96117916A CN 1064197 C CN1064197 C CN 1064197C
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
- H03L7/189—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop comprising a D/A converter for generating a coarse tuning voltage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
Abstract
A PLL in a Frequency-Hopping mode communication system, includes: a digital storage buffer; a digital/analog converter; a voltage controlled oscillator; a variable divider; a phase comparator; a low-pass filter; a level detector; a controller for changing and reading the series of control voltage stored in the buffer and supplied to the digital/analog converter when performing transmitting/receiving, and selectively storing control voltage refered to Frequency-Hopping frequency until the digital signal is in a predetermined range, and for supplying the stored control voltage to the digital/analog converter when performing transmitting/receiving.
Description
The present invention relates to be used for a kind of phase-locked loop of communication system of frequency hopping type, particularly be used for improving locking time of prolonging by voltage controlled oscillator component deviation (component deviation) and the phase-locked loop of the drift that causes by environment change.The present invention is based on the korean application that application number is No.56544/1995, this application is included in this as a reference.
Phase-locked loop (below be called PLL) is a kind of automatic control circuit, be used to handle an output frequency of oscillation, so that make it synchronous or identical with an input signal or reference oscillator output signal fully with an input signal or reference oscillator output signal frequency.Generally, this PLL comprises a phase comparator (or phase detectors), a low pass filter and a voltage controlled oscillator, and they combine feedback control loop of formation.
Fig. 1 illustrates the general structure of this PLL.In Fig. 1, the frequency of oscillation of voltage controlled oscillator 104 is added to phase comparator 102 then by a variable demultiplier demultiplication.This phase comparator 102 will be compared by the phase place of the phase place of the frequency of oscillation of demultiplication with the reference signal that is produced by a reference signal generator 101, and produce phase signal to a low pass filter 103 according to comparative result.In case when the signal of this phase comparator 102 outputs is applied to voltage controlled oscillator 104 by filter 103, the phase place of this voltage controlled oscillator 104 will change.Then, reference signal that is produced by this reference signal generator 101 of these voltage controlled oscillator 104 usefulness produces the locking phase signal, as an output frequency fvco.
In above-mentioned PLL, the phase noise characteristic of this voltage controlled oscillator 104 and with locking time of the PLL of reference signal locking mainly by low pass filter 103 decisions.That is,, will improve the locking time of this PLL, but owing to be applied to the noise increase of this voltage controlled oscillator 104, phase noise characteristic degenerates if the bandwidth of this low pass filter 103 is widened by adjusting time constant.On the other hand,, improved the phase noise characteristic of voltage controlled oscillator thus if the bandwidth of this low pass filter 103 narrows down, but step-down locking time of this PLL.
, be fixed on a value therebetween, and voltage controlled oscillator 104 only exports in the system of a frequency of oscillation, do not cause very big trouble the locking time of this PLL in the demultiplication value of variable demultiplier 105.Yet thereby in by the system that changes variable demultiplier change voltage controlled oscillator 104 output frequencies of oscillation, shorten the locking time of PLL.For example, the multichannel radio telephone of a kind of use or a kind of portable phone, or use a kind of system requirements of frequency-hopping mode to have fast locking time and voltage controlled oscillator have good phase noise characteristic.
A kind of method of recommending according to such requirement is disclosed in the title of announcement on December 25 nineteen ninety in the U.S. Pat 4,980,652 of " frequency synthesizer with nonlinear compensation ".This patent (US4,980,652) instruction: a control voltage corresponding to an output frequency that obtains in this voltage controlled oscillator is stored in the read-only memory (to call ROM in the following text) in advance.This magnitude of voltage is used as a control voltage of this voltage controlled oscillator then.In addition, use offset compensation block to calculate and a subtractor block, compensate from the error amount that this low pass filter extracts, so that as this control voltage of voltage-controlled oscillator according to for example time and these environmental changes of temperature.Like this, by using a kind of indirect compensation method, above-mentioned patent US4,980,652 have improved the characteristic of locking time and phase noise, this direct compensation method is to be added to this voltage controlled oscillator and to control voltage as it being stored in magnitude of voltage among this ROM in advance, controls voltage and also be added to this voltage controlled oscillator by the magnitude of voltage of this subtractor block compensation as it.
Wherein, in the voltage controlled oscillator of the 900MHz of commercially available portable telephone frequency band, the output frequency skew that is caused by variation of ambient temperature is generally ± 2MHz, and the output frequency that is caused by the component deviation under the fixedly control voltage conditions of normal temperature skew is about ± 5MHz.In other words, according to voltage controlled oscillator component deviation and for example in the environmental change of time and ambient temperature, output frequency is offset greater than thousands of PPM (a few millionths).When passing through to use when disclosed a kind of indirect compensation method in the above-mentioned patent 4,980,652 reduces such output frequency skew on thousands of PPM, this system configuration and calculating become complicated, and compensating error will increase.
The recommended other method that is used to improve PLL locking time and phase noise of voltage controlled oscillator characteristic is disclosed in the title announced on October 11st, 1994 U.S. Pat 5 for " adopting memory to deposit to be used to the phase-locked loop of the control data of controlling frequency of oscillation ", in 355,098.Above-mentioned patent (US5,355,098) instruction: before this PLL outage, will be added to this control voltage of voltage-controlled oscillator immediately and be stored in the memory, and when this PLL is powered up again, the control voltage that is stored in this memory is used as this control voltage of voltage-controlled oscillator, improves the locking time of the phase noise characteristic and the PLL of voltage controlled oscillator thus.Yet, though make in this way, if through long-time or variation of ambient temperature is unexpected, according to the output frequency skew of voltage controlled oscillator environmental change greater than thousands of PPM.That is, because this PLL has the error range that is caused by a big frequency shift (FS) during initial phase lock, the characteristic of the locking time of this PLL degenerates.For example, very important when the component deviation of long-time this voltage controlled oscillator after PLL is de-energized, perhaps ought move to another ambient temperature place very inequality, if the power connection of PLL, it will be significant relying in the output frequency skew of environmental change.Therefore need one and remove to lock this initial phase for a long time.
The title that recommended another method that solves a kind of like this problem is disclosed in application in December nineteen ninety-five is the korean patent application No.95-64216 of " being used for improving the phase-locked loop of phase locking time ", transfers the possession of the assignee identical with the present invention.Fig. 2 is illustrated in disclosed structure among the above-mentioned patent application No.95-64216.PLL that Fig. 2 describes a radio communications system send out or the operation of the pattern of receipts carry out before the frequency computation part control voltage in each operator scheme, needing immediately.The control voltage that calculates is used in the operator scheme of a reality, so that improve because of the component deviation of voltage controlled oscillator and the locking time that is prolonged by the skew that environment change causes.Therefore, if a kind of like this PLL uses in using multichannel radio telephone and portable phone or in the communication system of frequency hopping, it will satisfy the fast frequency change of needs in each system.
But, exist difference between the characteristic that needs in the communication system of the frequency-hopping mode that this specific character that requires and for example WLAN (local area network (LAN)) are such in the typical cellular telephone machine.O.1PPM the skew of the output frequency of the voltage controlled oscillator of this typical cellular telephone machine is lower than, and the frequency shift (FS) of the voltage controlled oscillator of this communication system of frequency hopping type may be allowed and is lower than 25PPM.The data of this communication system of frequency hopping type are pressed the transmission of Mbps unit in addition, and the data of portable phone are pressed the transmission of Kbps unit.The effect unit millisecond (ms) of send out/bringing drill to an end that is portable phone is implemented, and the effect unit microsecond (μ s) of send out/bringing drill to an end of communication system of frequency hopping type is finished.
Because this communication system of frequency hopping type has characteristic as mentioned above, the structure that is suitable for the PLL of this communication system of frequency hopping type needn't intactly be used structure as shown in Figure 2.If PLL as shown in Figure 2 is applied to the frequency hopping communication system, can improve by voltage controlled oscillator component difference and because the PLL locking time that the frequency shift (FS) that environment change causes is extended by structure and the control operation of simplifying this PLL shown in Figure 2.
The object of the present invention is to provide a kind of PLL that is suitable for communication system of frequency hopping type.
Another object of the present invention is to provide and do when send out/bringing drill to an end and be used to make the component deviation of voltage controlled oscillator and a kind of PLL that is reduced to minimum by the frequency deviation that environmental change causes when carrying out not according to communication system of frequency hopping type.
For reaching above purpose, a kind of like this PLL is provided, be used for by not storing a control voltage when doing and be used for frequency of utilization when carrying out send out/to bring drill to an end, and when execution this/the control voltage that will store in advance when doing of bringing drill to an end is applied to voltage controlled oscillator to be improved because of the component deviation of voltage controlled oscillator and the locking time that is prolonged by the skew that environmental change causes.
The PLL that a kind of the present invention of enforcement is used for communication system of frequency hopping type comprises: one first buffer is used for a series of control voltages of digital storage; One second buffer is connected to this first buffer; The digital control voltage transitions that one D/A is used for applying becomes an analog control voltage; One adder is used for the output of this D/A is appended to a bias voltage; One voltage controlled oscillator produces a frequency of oscillation according to the analog control voltage that is produced by this adder; One variable demultiplier is according to the output of a variable demultiplication than this voltage controlled oscillator of demultiplication; One phase comparator, the phase place that is used for the same reference signal of phase place of the signal that will be produced by this variable demultiplier is compared, and produces the phase signal that the result is compared in indication; One low pass filter is used for this phase signal of low-pass filtering; One level detector is used for the same reference level of an analog signal that is produced by this low pass filter is compared, and produces the digital signal of an expression comparative result; And control device, be used for send out/not bringing drill to an end when doing when carrying out, when changing and reading a series of control voltages that are stored in first buffer, if digital signal is in predetermined scope, to be stored in second buffer with the control voltage of the frequency dependence that is used for frequency hopping so that be added to D/A, and send out/bring drill to an end when doing when carrying out, the control voltage that is stored in second buffer is applied to this D/A.
This PLL can also be only with a buffer that is divided into two zones, alternative second buffer of control voltage that is used to store first buffer of a series of control voltages and is used to store and is used for the frequency dependence of frequency hopping.
Calculate the control magnitude of voltage of each frequency that is applied to frequency hopping mutually when not implementing when send out/bringing drill to an end, and send out/bring drill to an end do during the control voltage of this calculating of use, can reduce the locking time of this PLL regardless of component deviation and environmental change.
The present invention will be described in conjunction with the accompanying drawings in more detail, the components identical of equal reference numbers number indication in the accompanying drawings.
When in conjunction with the accompanying drawings with reference to following detailed description can understand better the present invention with and attached advantage, and this is to understand easily, wherein identical reference symbol is represented identical or similar elements, wherein:
Fig. 1 is the calcspar of the general PLL structure of expression;
Fig. 2 is the calcspar of PLL structure in the expression prior art;
Fig. 3 is the calcspar of expression by PLL structure of the present invention;
Fig. 4 A, 4B and 4C are that expression is used the operating time of communication system of frequency hopping type of the present invention and by the curve chart of operating time of PLL of the present invention;
Fig. 5 is the flow chart of expression by the write operation of PLL of the present invention;
Fig. 6 is the flow chart of expression by the read operation of PLL of the present invention;
Fig. 7 A be the expression general PLL locking time characteristic flow chart;
Fig. 7 B be the expression by PLL of the present invention locking time characteristic flow chart.
What should give attention is that the same letter reference number will be used to refer to the identical or equivalent element with identical function in whole accompanying drawing.In addition, in following explanation, with the detail of explanation numeral, for example, the concrete element of built-up circuit and frequency is understood the present invention better to provide.Yet this will be tangible with regard to can putting into practice those skilled in the art of the present invention for need not specific details.To avoid in the present invention and describing in detail about being helpless to understand the existing function and the structure of theme of the present invention.Following term is being considered function of the present invention and can be differing from each other aspect user or chip design people's intention, and they should define on the basis by this description.
Fig. 3 is the calcspar of expression by the structure of PLL of the present invention.
With reference to Fig. 3, do not have as switch included among Fig. 2 PLL 108.For the switch 108 of Fig. 2, be omissible to communication system of frequency hopping type.
Send out/bring drill to an end when doing when not carrying out, if the numerical data that is stored in first buffer 110 converts analog signal to and is added to voltage controlled oscillator 104 by an adder 112 by a D/A (D/A) transducer 111, then this voltage controlled oscillator 104 will produce oscillation frequency specific continuously.The output frequency of this voltage controlled oscillator 104 is added to phase comparator 102 by variable demultiplier 105.Phase comparator 102 is compared the output of variable demultiplier 105 with the reference signal that reference signal generator 101 produces, the phase signal of output expression comparative result, this demultiplier 105 is according to the frequency of oscillation of a variable demultiplication of being determined by second controller 106 than this voltage controlled oscillator 104 of demultiplication.Because this phase signal comprises many high frequencies and noise component(s), low pass filter 103 changes into this high frequency and noise component(s) one direct current (DC) component and this DC component is added to a level detector 113.Level detector 113 detects this phase signal whether in a specific scope by the analog signal of low pass filter 103 outputs and a predetermined reference level value are compared, and this testing result is added to first controller 107 as digital signal.These phase signals of first controller 107 check whether in specific scope, and two phase places of these two signals of oscillator signal by using the digital signal check reference signal that produces by level detector 113 and voltage controlled oscillator 104 who is faster.In addition this first controller 107 according to assay by the phase difference between the oscillator signal that increases or reduce the Data Control reference signal that is stored in first buffer 110 and voltage controlled oscillator 104 in this specific scope.If the phase difference between the oscillator signal of reference signal and voltage controlled oscillator 104 is within specific error range, then first controller 107 is stored in the corresponding data of first buffer 110 in first buffer 109.Because this second buffer 109 comprises that the data of being selected by first controller 107 can be stored in the corresponding address of second buffer 109 corresponding to a plurality of addresses of using each frequency in system in this first buffer 110.Do not produce any problem when frequency of utilization in system therebetween, after a little while.Yet when in this system, using many frequencies, can use calculator 114 effectively.If frequency is few, the data of corresponding all frequencies of utilization can be stored in second buffer 109.If but there are many frequencies, only estimate the frequency of right quantity, and other frequencies are calculated by using calculator 114, so that be stored in the appropriate address of second buffer 109.The data value of corresponding frequency of utilization can be by calculating, because the control voltage characteristic of this voltage controlled oscillator 104 is near linear.
If begin send out/to bring drill to an end work, the data that are stored in second buffer 109 convert analogue data to by D/A converter 111, and append to a given bias voltage by adder 112.Like this, this additional result is used as the control voltage of voltage controlled oscillator 104.At this moment, this bias voltage is a dc voltage, is used to proofread and correct the skew that produces and makes system become more convenient in circuit structure.
Fig. 4 A, 4B and 4C are that expression is used the operating time of communication system of frequency hopping type of the present invention and by the curve chart of operating time of PLL of the present invention.
With reference to Fig. 4 A, 4B and 4C, expression here is used to control the timing diagram of the signal of this communication system of frequency hopping type operation, and, determine by these signals by the operating time of PLL of the present invention.Fig. 4 A explanation is used to control the transmitter enabling signal TXE of firing operation.Like this, when this transmitter enabling signal TXE was in logic " height " level, system carried out firing operation.Fig. 4 B explanation is used to control the carrier sense signal CRS that receives operation.The carrier sense signal CRS representative of a logic " height " level is just receiving a signal.Fig. 4 C represents the time of unenforced of the system/work of bringing drill to an end, and, does not produce the time of transmitter initiating signal TXE and carrier sense signal CRS that is.During at this moment, PLL estimates the control voltage that uses the frequency in this system.
Fig. 5 is the flow chart of expression by the write operation of PLL of the present invention.When the signal in Fig. 4 C is in logic " height " level, promptly when system does not carry out any operation, carry out this write operation.
If energized, in step 502, whether 107 checks of first controller are carrying out the work of send out/bringing drill to an end.If first controller 107 turns back to step 502 then in step 504 delay a period of time.If promptly do not carry out this/work of bringing drill to an end, first controller 107 is provided with admissible deviant R in step 506 but if not.First controller 107 is provided with an initial value in step 508 in first buffer 110, and selects the frequency of a use in step 510.Here, the frequency of a use of selection means second controller 106 and will be applied to this variable demultiplier 105 corresponding to the variable demultiplication ratio of a frequency in the frequency of using in this system.If be provided to this variable demultiplier 105 by above definite variable demultiplication ratio, detect this phase difference in step 512, and in the compare operation of step 514 excute phase difference.That is, the output phase that phase comparator 102 will this variable demultiplier 105 is compared and the output phase difference signal with the output phase of reference signal generator 101.103 pairs of these phase signals of low pass filter carry out low pass filter.Level detector 113 will be compared and produce the digital signal of this comparative result of indication through the level of the level of the phase signal of low pass filter and reference signal.First controller 107 uses digital signal detection at frequency and the phase difference between the reference signal selected at present and check in the deviant R whether this phase difference allowing.
If phase difference is less than the deviant R of this permission, at the data of step 516 first controller 107 increases by first buffer 110, repeating step 512 and 514 then.On the contrary, if this phase difference greater than the deviant R of this permission, first controller 107 reduces data and repeating step 512 and 514 of first buffer 110 so.If this phase difference is in the deviant R that allows, then first controller 107 stores the corresponding data of first buffer 110 in second buffer 109.Till above-mentioned steps is repeated until that frequency to be estimated is chosen in step 522 and finishes, that is, and up to using the data of the frequency in this system to be stored in second buffer 109 corresponding to all.If the frequency of estimation is all selected, and the data storing of first buffer 110 is in second buffer 109, the control magnitude of voltage of the frequency of corresponding use (except that sampling frequency) calculates in step 524, and is stored in second buffer 109 at the control magnitude of voltage of this calculating of step 526.In this case, the control magnitude of voltage is calculated by calculator 114.In step 528, whether check is carrying out the work of send out/bringing drill to an end.If the carrier sense signal CRS of a transmitter enabling signal TXE or control signal indication produces the work of send out/bringing drill to an end, then above operation will stop.If the control signal of generation, first controller 107 postpones the given time and turns back to step 502 in step 530.
On the other hand, in Fig. 5, when after execution in step 502-526, control signal TXE or the indication send out/bring drill to an end the work CRS write operation when step 528 produces be terminated.Yet preferable is to stop write operation when producing when the CRS that does send out/is brought drill to an end in control signal TXE or indication, even carry out any operation.
Fig. 6 is the read operation of expression by PLL of the present invention.When producing, carries out the carrier sense signal CRS of transmitter enabling signal TXE that produces the indication firing operation or expression reception operation this read operation.
Receive the carrier sense signal CRS that operates if produce the transmitter enabling signal TXE or the indication of indicating firing operation, be stored in the data of the control magnitude of voltage in second buffer 109 to first buffer 110 in step 602 first controller 107 transmission correspondences.The data transaction that will be transferred to first buffer 110 at step 604D/A transducer 111 becomes analog control voltage.Adder 112 additional DC bias voltages are to this analog control voltage, and the value that should add be applied to voltage controlled oscillator 104.In step 606, according to output voltage controlled oscillator 104 these frequencies of generation of adder.
If this voltage controlled oscillator is controlled by said method, can be greatly improved shown in Fig. 7 B the locking time of general PLL shown in Fig. 7 A.
As noted before, PLL of the present invention is simple in structure, makes the component deviation of voltage controlled oscillator and the frequency shift (FS) minimum that is caused by environmental change.A kind of PLL like this is of great use in the frequency hopping communication system, for example requires the fast-changing WLAN of frequency.
Although represented and described the preferred embodiment of the present invention,, those skilled in the art is apparent that various changes and improvements all can carry out, do not depart from spirit of the present invention.For example, might use a storage device to substitute 2 buffers.In addition, the control magnitude of voltage that is used for frequency of utilization except that sampling frequency can be calculated by the alternative calculator of first controller.Therefore, it is open as the specific embodiment that is intended for use to realize best pattern of the present invention to be to be understood that the present invention is not limited at this, but the present invention is not limited to removing in additional certain embodiments beyond claim limited described in specification of the present invention.
Claims (4)
1. phase-locked loop that is used for communication system of frequency hopping type is characterized in that comprising:
One buffer is used to store the digital value corresponding to the control voltage of the frequency that is used for frequency hopping;
One D/A, the digital control voltage transitions that is used for applying becomes analog control voltage;
One voltage controlled oscillator is used for producing a frequency of oscillation according to the described aanalogvoltage by described D/A output;
One variable demultiplier is used for by the output of variable demultiplication than the described voltage controlled oscillator of demultiplication;
One phase comparator, the phase place that is used for the signal that will be produced by described variable demultiplier is compared with the phase place of reference signal, and produces the phase signal of indication comparative result;
One low pass filter is used for the described phase signal of low-pass filtering;
One level detector, the same reference level of level that is used for the analog signal that will be produced by described low pass filter is compared, and produces the digital signal of indication comparative result; And
One controller, be used for send out/not bringing drill to an end when doing when carrying out, read a series of control voltages of being stored in the described buffer and described control voltage is used for phase-locked loop, change described control voltage,, in a preset range, send out/bring drill to an end when doing up to the output of described level detector when carrying out, with the control store voltages of described change in described buffer, so that upgrade control voltage, and the control voltage of described storage is added to described D/A by frequency.
2. a kind of phase-locked loop as claimed in claim 1, when it is characterized in that level when the described digital signal that is produced by described level detector is less than described presetting range, described controller is carried out read operation by the described control magnitude of voltage that increase is stored in the described buffer, and, carry out this read operation by the described control magnitude of voltage that reduces to be stored in the described buffer when the described digital signal level that produces by described level detector during greater than described presetting range.
3. phase-locked loop that is used for communication system of frequency hopping type is characterized in that comprising:
One first buffer is used for digitally storing a series of control voltages;
One second buffer is connected to described first buffer;
One D/A, the digital control voltage transitions that is used for applying becomes an analog control voltage;
One adder is used for the output of described D/A is appended to a given bias voltage;
One voltage controlled oscillator is used for producing a frequency of oscillation according to the described control voltage that is produced by described adder;
One variable demultiplier is used for according to the output of a variable demultiplication than the described voltage controlled oscillator of demultiplication;
One phase comparator, the phase place that is used for the signal that will be produced by described variable demultiplier is compared with the phase place of reference signal, and the phase signal of output indication comparative result;
One low pass filter is used for the described phase signal of low-pass filtering;
One level detector is used for the same reference level of analog signal level that is produced by described low pass filter is compared, and the digital signal of output indication comparative result; And
One controller, be used for send out/not bringing drill to an end when doing when carrying out, read a series of control voltages of being stored in described first buffer and described control voltage is used for phase-locked loop, change described control voltage, up to the output of described level detector in a preset range, send out/bring drill to an end when doing when carrying out, with the control store voltages of described change in described second buffer, so that upgrade control voltage, and the control voltage that will be stored in described second buffer by frequency is added to described D/A.
4. a kind of phase-locked loop as claimed in claim 3, when it is characterized in that level when the said digital signal that is produced by said level detector is less than said presetting range, said controller is carried out read operation by the said control magnitude of voltage that increase is stored in the said buffer, and, carry out this read operation by the said control magnitude of voltage that reduces to be stored in the said buffer when the said digital signal level that produces by said level detector during greater than said presetting range.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR56544/95 | 1995-12-26 | ||
| KR1019950056544A KR100206462B1 (en) | 1995-12-26 | 1995-12-26 | Phase locked loop for frequency hopping communication |
| KR56544/1995 | 1995-12-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1156923A CN1156923A (en) | 1997-08-13 |
| CN1064197C true CN1064197C (en) | 2001-04-04 |
Family
ID=19444407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96117916A Expired - Fee Related CN1064197C (en) | 1995-12-26 | 1996-12-24 | Phase locked loop for communication system of frequency hopping type |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR100206462B1 (en) |
| CN (1) | CN1064197C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2379105B (en) * | 2001-08-24 | 2003-07-09 | Roke Manor Research | Improvements relating to fast frequency-hopping modulators and demodulators |
| CN103138753B (en) * | 2011-11-23 | 2016-08-10 | 联想(北京)有限公司 | Adjusting means, phaselocked loop, electronic equipment, bandwidth adjusting method and device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US547714A (en) * | 1895-10-08 | Time-controlled electric heater | ||
| US5389899A (en) * | 1991-08-30 | 1995-02-14 | Fujitsu Limited | Frequency synthesizer having quick frequency pull in and phase lock-in |
| US5444420A (en) * | 1994-09-29 | 1995-08-22 | Harris Corporation | Numerically controlled phase lock loop synthesizer/modulator and method |
-
1995
- 1995-12-26 KR KR1019950056544A patent/KR100206462B1/en not_active IP Right Cessation
-
1996
- 1996-12-24 CN CN96117916A patent/CN1064197C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US547714A (en) * | 1895-10-08 | Time-controlled electric heater | ||
| US5389899A (en) * | 1991-08-30 | 1995-02-14 | Fujitsu Limited | Frequency synthesizer having quick frequency pull in and phase lock-in |
| US5444420A (en) * | 1994-09-29 | 1995-08-22 | Harris Corporation | Numerically controlled phase lock loop synthesizer/modulator and method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970057057A (en) | 1997-07-31 |
| CN1156923A (en) | 1997-08-13 |
| KR100206462B1 (en) | 1999-07-01 |
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