KR970056138A - Timing Control Circuit of Integrated Information Communication Network Line Interface Circuit - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

A line interface circuit of a video conference control system.

2. The technical problem to be solved by the invention

In the case where two or more ISDN lines are connected, the present invention provides a timing control circuit that receives a reference clock from one of the lines and absorbs a phase difference from the other line based on this clock to prevent synchronization misalignment.

3. Summary of Solution to Invention

A circuit for controlling the operation timing of a comprehensive information communication network line interface circuit having a large number of SSs is divided into a 16.384 MHz master clock provided from the outside and a 512KHz clock from the plurality of ISs to divide a clock of 8KHz. Means for outputting an internal clock signal of 8 KHz for synchronizing each SS by compensating the phase of the divided signal, and means for correcting the frequency of the master clock by the phase compensated signal; And means for generating a clock of 2.048 MHz by dividing the frequency-corrected signal by eight. The 2.048 MHz clock is divided by 256 and fed back to the phase compensating means.

4. Important uses of the invention

It can be used to control the timing in implementing a video conferencing control system that can conduct video conferencing simultaneously between multiple points.

Description

Timing Control Circuit of Integrated Information Communication Network Line Interface Circuit

Since this is an open matter, no full text was included.

1 is a block diagram of a comprehensive information communication network line interface circuit according to the present invention.

2 is a diagram showing a relationship between a timing control circuit and a first to third ISAC in FIG.

Claims (4)

Interface means for exchanging data with a computer, a plurality of ISCs connected to a comprehensive information network line for connecting 2-bit data by a de-channel protocol, and an arbitrary input stream to an arbitrary output stream to a channel. A timing control circuit of a general information and communication network line interface circuit having a space-time switch that can be exchanged with a channel so as to enable terminal connection between multiple points, the externally provided master clock of 16.384 MHz and the plurality of SS Subsidiary means for dividing a clock of 512KHz from the clock to produce an 8KHz clock, means for compensating the phase of the divided signal and outputting an internal clock signal of 8KHz for synchronizing each of the CSs, and the phase-compensated signal Means for correcting the frequency of the master clock by And means for generating a 2.048 MHz clock divided by 8. 2. The circuit according to claim 1, further comprising means for dividing said 2.048 MHz clock by 256 to feed back to said phase compensating means. 2. The circuit of claim 1, wherein the plurality of ISCs extract timings from the exchange through the u-interface, and restore and use the system framing and clock provided through the es-bus interface. 4. The circuit according to claim 3, wherein the plurality of SS operates in synchronization with a line clock of 192 KHz when transmitting and receiving data. ※ Note: The disclosure is based on the initial application.