KR970055373A - Comparator Circuit Controls the Size of Hysteresis - Google Patents

Comparator Circuit Controls the Size of Hysteresis Download PDF

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Publication number
KR970055373A
KR970055373A KR1019950053378A KR19950053378A KR970055373A KR 970055373 A KR970055373 A KR 970055373A KR 1019950053378 A KR1019950053378 A KR 1019950053378A KR 19950053378 A KR19950053378 A KR 19950053378A KR 970055373 A KR970055373 A KR 970055373A
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South Korea
Prior art keywords
node
signal
output
amplifying means
current
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KR1019950053378A
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Korean (ko)
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KR0177997B1 (en
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장천섭
장경희
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김광호
삼성전자 주식회사
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Priority to KR1019950053378A priority Critical patent/KR0177997B1/en
Publication of KR970055373A publication Critical patent/KR970055373A/en
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Publication of KR0177997B1 publication Critical patent/KR0177997B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0233—Bistable circuits
    • H03K3/02337—Bistables with hysteresis, e.g. Schmitt trigger

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

본 발명은 히스테리시스를 가진 비교기 회로에 관한 것으로서, 특히, 히스테리시스를 간단하면서도 정확하게 제어할 수 있는 비교기 회로에 관한 것이다.The present invention relates to a comparator circuit having hysteresis, and more particularly, to a comparator circuit capable of controlling the hysteresis simply and accurately.

본 발명은 입력 신호와 기준 신호의 차를 증폭하여 출력하는 차동 증폭 수단; 상기 차동 증폭 수단의 제2노드에서 출력하는 신호의 변화에 따라 상기 기준 신호를 반비례하도록 변동 시키는 기준전압 발생부; 및 상기 차동 증폭 수단의 제2노드에서 신호의 변화에 따라 버퍼링하여 출력 신호를 출력하는 출력 수단을 구비한 것을 특징으로 하여 공정 산포의 영향을 받지 않고, 기준 전압의 전위를 하도록 하여 비교기의 히스테리-시스를 간단하면서도 정확하게 제어할 수 있다.The present invention provides differential amplification means for amplifying and outputting a difference between an input signal and a reference signal; A reference voltage generator for varying the reference signal in inverse proportion to a change in the signal output from the second node of the differential amplifying means; And output means for outputting an output signal by buffering the signal at the second node of the differential amplification means according to the change of the signal. The sheath can be controlled simply and accurately.

Description

히스테리시스의 크기를 제어할 수 있는 비교기 회로Comparator Circuit Controls the Size of Hysteresis

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 비교기 회로의 상세 회로도이다.2 is a detailed circuit diagram of a comparator circuit according to the present invention.

제3도는 본 발명에 따른 비교기 회로의 동작 파형도이다.3 is an operational waveform diagram of a comparator circuit according to the present invention.

Claims (4)

입력 신호와 기준 신호의 차를 증폭하여 출력하는 차동 증폭수단; 상기 차동 증폭 수단의 제2노드에서 출력하는 신호의 변화에 따라 상기 기준 신호를 반비례하도록 변동시키는 기준 전압 발생부; 및 상기 차동 증폭 수단의 제2노드에서 출력되는 신호의 변화에 따라 상기 기준 신호를 반비례하도록 변동 시키는 기준 전압발생부; 및 상기 차동 증폭 수단의 제2노드에서 출력하는 신호의 변화에 따라 버퍼링하여 출력 신호를 출력하는 출력 수단을 구비한 것을 특징으로 하는 히스테리시스의 크기를 제어할 수 있는 비교기 회로.Differential amplifying means for amplifying and outputting a difference between an input signal and a reference signal; A reference voltage generator for varying the reference signal in inverse proportion to a change in the signal output from the second node of the differential amplifying means; And a reference voltage generator for changing the reference signal in inverse proportion to a change in the signal output from the second node of the differential amplifying means. And output means for buffering and outputting an output signal according to a change in the signal output from the second node of the differential amplifying means. 제1항에 있어서, 상기 기준 전압 발생부는 상기 차동 증폭 수단의 제2노드에서 출력하는 신호 변화에 따라 변화되는 전류를 제1노드에 전달하는 신호 레벨 변환부; 및 기준 전압을 발생하는 기준 전압 발생기로 구성된 것을 특징으로 하는 히스테리시스의 크기를 제어할 수 있는 비교기 회로.The apparatus of claim 1, wherein the reference voltage generator comprises: a signal level converter configured to transfer a current changed according to a signal change output from the second node of the differential amplifying means to the first node; And a reference voltage generator for generating a reference voltage. A comparator circuit capable of controlling a magnitude of hysteresis. 제2항에 있어서, 상기 신호 레벨 변환부는 일정한 제1전류를 흐르도록 하는 제1전류원; 상기 제1정전류원과 상기 제1노드 사이에 연결되어 전류의 패스가 되며 역전류를 방지하는 다이오드; 상기 차동 증폭 수단의 제2노드에서 출력되는 신호의 응답하여 상기 제1정전류원의 전류를 흐르도록 하는 트랜지스터; 및 상기 트랜지스터와 상기 차동 증폭 수단의 제2노드 사이에 연결된 제1저항을 구비한 것을 특징으로 하는 히스테리시스의 크기를 제어할 수 있는 비교기 회로.The apparatus of claim 2, wherein the signal level converting unit comprises: a first current source configured to flow a constant first current; A diode connected between the first constant current source and the first node to pass a current and prevent a reverse current; A transistor for flowing a current of the first constant current source in response to a signal output from the second node of the differential amplifying means; And a first resistor coupled between the transistor and a second node of the differential amplifying means. 제2항에 있어서, 상기 기준 전압 발생기는 일정한 제2전류를 제1노드에 흐르도록 하는 제2전류원; 및 상기 제1노드와 접지 사이에 전압 변화를 위한 제1저항이 연결된 것을 특징으로 하는 히스테리시스의 크기를 제어할 수 있는 비교기 회로.3. The apparatus of claim 2, wherein the reference voltage generator comprises: a second current source for flowing a constant second current to the first node; And a first resistor for changing the voltage between the first node and the ground, the comparator circuit capable of controlling the magnitude of the hysteresis. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950053378A 1995-12-21 1995-12-21 Comparator Circuit Controls the Size of Hysteresis KR0177997B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950053378A KR0177997B1 (en) 1995-12-21 1995-12-21 Comparator Circuit Controls the Size of Hysteresis

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950053378A KR0177997B1 (en) 1995-12-21 1995-12-21 Comparator Circuit Controls the Size of Hysteresis

Publications (2)

Publication Number Publication Date
KR970055373A true KR970055373A (en) 1997-07-31
KR0177997B1 KR0177997B1 (en) 1999-04-01

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100873287B1 (en) * 2002-02-26 2008-12-11 매그나칩 반도체 유한회사 Comparator with Hysteresis Characteristics

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