KR970054537A - Method of manufacturing double peak resonance transmissive diode - Google Patents

Method of manufacturing double peak resonance transmissive diode Download PDF

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KR970054537A
KR970054537A KR1019950050516A KR19950050516A KR970054537A KR 970054537 A KR970054537 A KR 970054537A KR 1019950050516 A KR1019950050516 A KR 1019950050516A KR 19950050516 A KR19950050516 A KR 19950050516A KR 970054537 A KR970054537 A KR 970054537A
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layer
gaas
electrode
mesa
impurities
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KR0170486B1 (en
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추혜용
유병수
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양승택
한국전자통신연구원
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
    • H10D30/4738—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material having multiple donor layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10336—Aluminium gallium arsenide [AlGaAs]

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

본 발명은 이중 피크 공명 투과 다이오드의 제조방법에 관한 것으로, 반절연성 GaAs의 반도체 기판 상에 N형 불순물이 많이 도핑된 GaAs의 버퍼층, N형 불순물이 약간 도핑된 GaAs의 제1간격층, 불순물이 도핑되지 않은 AlGaAs의 제1장벽층, 불순물이 도핑되지 않은 GaAs의 우물층, 불순물이 도핑되지 않은 AlGaAs의 제2장벽층, N형 불순물이 약간 도핑된 GaAs의 제2간격층, N형 불순물이 많이 도핑된 GaAs의 접촉층을 순차적으로 결정 성장하는 공정과, 상기 버퍼층이 노출되도록 상기 접촉층 부터 버퍼층 까지 소정 부분을 건식 식각하여 메사 형태를 형성하는 공정과, 상기 버퍼층의 노출된 부분의 상부와 상기 접촉층 상부의 일측에 각각 제1 및 제2전극을 형성하는 공정과, 상술한 구조의 전 표면에 절연막을 증착한 후 메사 상부의 제2전극 및 접촉층과 메사 하부의 제1전극을 노출시키는 공정과, 상기 제2전극과 설연막을 마스크로 하여 상기 접촉층의 노출된 부분을 식각하고 상기 제1 및 제2전극 상에 도전성 금속을 증착하여 본딩 패드를 형성하는 공정을 구비한다. 따라서, 메사위에 형성된전극의 면적을 메사보다 작게하고전극이 형성되지 않는 접촉층을 부분적으로 식각하므로서 전압 강하의 차를 유도하여 전극이 형성된 영역과 형성되지 않은 영역의 이중 장벽 양자 우물 구조의 공명 투과 조건을 다르게 하여 간단하게 두개의 피크를 도출할 수 있어 고집적을 이룰 수 있다.The present invention relates to a method for manufacturing a double peak resonance transmission diode, wherein a buffer layer of GaAs heavily doped with N-type impurities, a first gap layer of GaAs slightly doped with N-type impurities, and impurities are formed on a semi-insulating GaAs semiconductor substrate. The first barrier layer of undoped AlGaAs, the well layer of GaAs undoped with impurities, the second barrier layer of AlGaAs undoped with impurities, the second gap layer of GaAs slightly doped with N-type impurities, Crystally growing a contact layer of heavily doped GaAs, dry etching a predetermined portion from the contact layer to the buffer layer so as to expose the buffer layer, and forming a mesa form, and an upper portion of the exposed portion of the buffer layer Forming first and second electrodes on one side of the upper contact layer, and depositing an insulating film on the entire surface of the above-described structure, and then forming the second electrode and the contact layer on the mesa and the lower part of the mesa. Exposing a first electrode and etching the exposed portion of the contact layer using the second electrode and the snow lead layer as a mask and depositing a conductive metal on the first and second electrodes to form a bonding pad. do. Therefore, the area of the electrode formed on the mesa is smaller than that of the mesa, and the portion of the contact layer where the electrode is not formed is partially etched to induce a difference in voltage, thereby resonating the double barrier quantum well structure between the region where the electrode is formed and the region that is not formed By varying the conditions, two peaks can be derived simply, resulting in high integration.

Description

이중 피크 공명 투과 다이오드의 제조방법Method of manufacturing double peak resonance transmissive diode

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도(a)에서 (e)는 본 발명에 의한 이중피크공명투과다이오드 제작방법.Figure 3 (a) to (e) is a double peak resonance transparent diode manufacturing method according to the present invention.

Claims (6)

반절연성 GaAs의 반도체 기판 상에 N형 불순물이 많이 도핑된 GaAs의 버퍼층, N형 불순물이 약간 도핑된 GaAs의 제1간격층, 불순물이 도핑되지 않은 AlGaAs의 제1장벽층, 불순물이 도핑되지 않은 GaAs의 우물층, 불순물이 도핑되지 않은 AlGaAs의 제2장벽층, N형 불순물이 약간 도핑된 GaAs의 제2간격층, N형 불순물이 많이 도핑된 GaAs의 접촉층을 순차적으로 결정 성장하는 공정과, 상기 버퍼층이 노출되도록 상기 접촉층부터 버퍼층까지 소정 부분을 식각하여 메사 형태를 형성하는 공정과, 상기 버퍼층의 노출된 부분의 상부와 상기 접촉층 상부의 일측에 각각 제1 및 제2전극을 형성하는 공정과, 상술한 구조의 전 표면에 절연막을 증착한 후 메사 상부의 제2전극 및 접촉층과 메사 하부의 제1전극을 노출시키는 공정과, 상기 제2전극과 절연막을 마스크로 하여 상기 접촉층의 노출된 부분을 식각하고 상기 제1 및 제2전극 상에 도전성 금속을 증착하여 본딩 패드를 형성하는 공정을 구비하는 이중 피크 공명 투과 다이오드의 제조방법.Buffer layer of GaAs heavily doped with N-type impurity on semiconductor substrate of semi-insulating GaAs, first gap layer of GaAs slightly doped with N-type impurity, first barrier layer of AlGaAs without dopant, impurity not doped Crystal growth of a GaAs well layer, a second barrier layer of AlGaAs not doped with impurities, a second gap layer of GaAs slightly doped with N-type impurities, and a contact layer of GaAs heavily doped with N-type impurities; Forming a mesa form by etching a predetermined portion from the contact layer to the buffer layer so that the buffer layer is exposed; and forming first and second electrodes on the exposed portion of the buffer layer and on one side of the upper contact layer, respectively. And depositing an insulating film on the entire surface of the structure described above, exposing the second electrode and the contact layer on the mesa and the first electrode on the bottom of the mesa, and using the second electrode and the insulating film as a mask. Etching the exposed portion of chokcheung and method for producing the first and second electrodes by depositing a conductive metal on a double-peak resonance and a step of forming a bonding pad, the transmitting diode. 제1항에 있어서, 상기 결정 성장층들을 MBE 또는 MOCVD 방법으로 형성하는 이중 피크 공명 투과 다이오드의 제조방법.The method of claim 1, wherein the crystal growth layers are formed by MBE or MOCVD. 제1항에 있어서, 상기 제2간격층을 불순물이 1× 1017∼5×1017cm-3로 도핑되게 형성하는 이중 피크 공명 투과 다이오드의 제조방법.The method of claim 1, wherein the second gap layer is formed such that impurities are doped with 1 × 10 17 to 5 × 10 17 cm −3 . 제3항에 있어서, 상기 제2간격층을 100∼150nm의 두께로 형성하는 이중 피크공명 투과 다이오드의 제조방법.4. The method of claim 3, wherein the second gap layer is formed to a thickness of 100 to 150 nm. 제1항에 있어서, 상기 접촉층을 불순물이 1× 1018∼5×1018cm-3의 고농도로 도핑되게 형성하는 이중 피크 공명 투과 다이오드의 제조방법.The method of claim 1, wherein the contact layer is formed to be doped with impurities at a high concentration of 1 × 10 18 to 5 × 10 18 cm −3 . 제1항에 있어서, 상기 메사의 상부와 제2전극의 면적 비는 1.5∼3:1 정도인 이중 피크 공명투과 다이오드의 제조방법.The method of claim 1, wherein an area ratio of the upper portion of the mesa to the second electrode is about 1.5 to about 3: 1. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950050516A 1995-12-15 1995-12-15 Fabrication method of double peak resonant tunneling diode KR0170486B1 (en)

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