KR970053920A - Manufacturing method of CMOS transistor - Google Patents

Manufacturing method of CMOS transistor Download PDF

Info

Publication number
KR970053920A
KR970053920A KR1019950066922A KR19950066922A KR970053920A KR 970053920 A KR970053920 A KR 970053920A KR 1019950066922 A KR1019950066922 A KR 1019950066922A KR 19950066922 A KR19950066922 A KR 19950066922A KR 970053920 A KR970053920 A KR 970053920A
Authority
KR
South Korea
Prior art keywords
region
spacer
conductive layer
plate
conductivity type
Prior art date
Application number
KR1019950066922A
Other languages
Korean (ko)
Inventor
김태성
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950066922A priority Critical patent/KR970053920A/en
Publication of KR970053920A publication Critical patent/KR970053920A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

NMOS 트랜지스터와 PMOS 트랜지스터를 함께 구비하는 씨모스(CMOS) 트랜지스터의제조방법에 대해 기재하고 있다. 이는, 활성영역 및 비활성영역으로 분리되어진 반도체 기판 상에, 게이트 전극, 절연층, 반도체 기판과 접촉하는 스토리지 전극, 유전막 및 플레이트 도전층을 차례로 형성하는 단계, 제1영역의 플레이트 도전층을 노출시키는 단계, 노출된 영역의 플레이트 도전층 및 절연층을 이방성 식각하여 플레이트전극을 형성함과 동시에, 제1영역의 게이트전극의 측벽에 제1스페이서를 형성하는 단계, 노출된 제1영역의 기판에 제1도전형의 불순물을 고농도로 주입하여 제1스페이서에 자기 정합된 제1도전형의 소오스/드레인을 형성하는 단계, 제2영역이 플레이트 도전층을 노출시키는 단계, 노출된 영역의 플레이트 도전층 및 절연층을 이방성 식각하여 제2영역의 게이트전극의 측벽에 제2스페이서를 형성하는 단계 및 포토레지스터 패턴을 이온주입 마스크로 사용하여 노출된 영역의 기판에 제2도전형의 불순물을 이온주입하여, 제2스페이서에 자기전합된 제2도전형의 소오스/드레인을 형성하는 단계를 포함한다.A method of manufacturing a CMOS transistor including an NMOS transistor and a PMOS transistor is described. This is performed by sequentially forming a gate electrode, an insulating layer, a storage electrode in contact with the semiconductor substrate, a dielectric layer, and a plate conductive layer on the semiconductor substrate separated into an active region and an inactive region, thereby exposing the plate conductive layer of the first region. Anisotropically etching the plate conductive layer and the insulating layer of the exposed region to form a plate electrode, and at the same time to form a first spacer on the sidewall of the gate electrode of the first region, the substrate on the exposed first region Implanting a highly conductive impurity of a first conductivity type to form a source / drain of the first conductivity type self-aligned to the first spacer, exposing the plate conductive layer to a second region, a plate conductive layer of the exposed region, and Anisotropically etching the insulating layer to form a second spacer on the sidewall of the gate electrode of the second region, and using the photoresist pattern as an ion implantation mask. And a step of ion-implanting a second impurity of the conductivity type to the substrate of the exposed region, forming a source / drain of the second conductivity type the sum jagijeon the second spacer.

따라서, 공정을 단순화할 수 있고, 스페이서 길이의 변화를 방지할 수 있다.Therefore, the process can be simplified and the change of the spacer length can be prevented.

Description

씨모스(CMOS) 트랜지스터의 제조방법Manufacturing method of CMOS transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2E도는 본 발명에 의한 씨모스(CMOS) 트랜지스터의 제조공정을 순서에 따라 도시한 단면도들이다.2A through 2E are cross-sectional views sequentially illustrating a manufacturing process of a CMOS transistor according to the present invention.

Claims (4)

활성영역 및 비활성영역으로 분리되어진 반도체기판상에, 게이트전극, 절연층, 상기 반도체 기판과 접촉하는 스토리지 전극, 유전막 및 플레이트 도전층을 차례로 형성하는 단계; 제1영역의 플레이트 도전층을 노출시키는 단계; 상기 노출된 영역의 플레이트 도전층 및 절연층을 이방성 식각하여 플레이트 전극을 형성함과 동시에, 제1영역의 게이트전극의 측벽에 제1스페이서를 형성하는 단계; 노출된 제1영역의 기판에 제1도전형의 불순물을 고농도로 주입하여 상기 제1스페이서에 자기정합된 제1도전형의 소오스/드레인을 형성하는 단계; 제2영역의 플레이트 도전층을 노출시키는 단계; 노출된 영역의 상기 플레이트 도전층 및 절연층을 이방성 식각하여 제2영역의 게이트전극의 측벽에 제2스페이서를 형성하는 단계; 및 상기 포토레지스트 패턴을 이온주입 마스크로 사용하여 노출된 영역의 기판에 제2도전형의 불순물을 이온주입하여, 상기 제2스페이서에 자기정합된 제2도전형의 소오스/드레인을 형성하는 단계를 포함하는 것을 특징으로 하는 씨모스(CMOS) 트랜지스터의 제조방법.Sequentially forming a gate electrode, an insulating layer, a storage electrode in contact with the semiconductor substrate, a dielectric layer, and a plate conductive layer on the semiconductor substrate separated into an active region and an inactive region; Exposing the plate conductive layer in the first region; Anisotropically etching the plate conductive layer and the insulating layer of the exposed region to form a plate electrode and simultaneously forming a first spacer on the sidewall of the gate electrode of the first region; Implanting impurities of a first conductivity type in a high concentration into the exposed first substrate to form a source / drain of a first conductivity type that is self-aligned to the first spacer; Exposing a plate conductive layer in a second region; Anisotropically etching the plate conductive layer and the insulating layer in the exposed region to form a second spacer on the sidewall of the gate electrode of the second region; And implanting impurities of a second conductivity type into a substrate in an exposed region by using the photoresist pattern as an ion implantation mask to form a second conductive source / drain self-aligned to the second spacer. Method of manufacturing a CMOS transistor comprising a. 제1항에 있어서, 상기 제1도전형은 N형이고, 제2도전형은 P형인 것을 특징으로 하는 씨모스(CMOS) 트랜지스터의 제조방법.The method of claim 1, wherein the first conductive type is N type and the second conductive type is P type. 제1항에 있어서, 상기 제1도전형의 소오스/드레인은 제1도전형의 불순물을 1.0E15/㎤ ∼8.0E15/㎤ 정도로 이온주입함으로써 형성되는 것을 특징으로 하는 씨모스(CMOS) 트랜지스터의 제조방법.The CMOS transistor of claim 1, wherein the source / drain of the first conductive type is formed by ion implantation of impurities of the first conductive type of about 1.0E15 / cm3 to 8.0E15 / cm3. Way. 제1항에 있어서, 상기 제1 및 제2스페이서는 그 폭을 서로 동일하게 형성하거나, 습식식각을 이용하여 서로 상이하게 형성하는 것을 특징으로 하는 씨모스(CMOS) 트랜지스터의 제조방법.The method of claim 1, wherein the first and second spacers are formed to have the same width or differently from each other using wet etching. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950066922A 1995-12-29 1995-12-29 Manufacturing method of CMOS transistor KR970053920A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950066922A KR970053920A (en) 1995-12-29 1995-12-29 Manufacturing method of CMOS transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950066922A KR970053920A (en) 1995-12-29 1995-12-29 Manufacturing method of CMOS transistor

Publications (1)

Publication Number Publication Date
KR970053920A true KR970053920A (en) 1997-07-31

Family

ID=66637862

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950066922A KR970053920A (en) 1995-12-29 1995-12-29 Manufacturing method of CMOS transistor

Country Status (1)

Country Link
KR (1) KR970053920A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080061060A (en) * 2006-12-28 2008-07-02 전자부품연구원 Unit pixel for use in cmos image sensor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080061060A (en) * 2006-12-28 2008-07-02 전자부품연구원 Unit pixel for use in cmos image sensor

Similar Documents

Publication Publication Date Title
KR940027104A (en) Transistor Manufacturing Method
KR960024604A (en) Dual channel thin film transistor and its manufacturing method
KR980006542A (en) Semiconductor device manufacturing method
KR970072204A (en) Circuit device having at least one MOS transistor and method of manufacturing the same
KR960009168A (en) Method of manufacturing semiconductor device with MOS structure and CMOS structure
KR970053920A (en) Manufacturing method of CMOS transistor
US6013554A (en) Method for fabricating an LDD MOS transistor
KR970077357A (en) Manufacturing method of MOS transistor
KR960026459A (en) Transistor Manufacturing Method
KR970024283A (en) MOS transistor and manufacturing method thereof
KR930001457A (en) MOS transistor and manufacturing method thereof
KR970054398A (en) Most transistor manufacturing method
KR950009978A (en) Manufacturing method of morph transistor
KR980005893A (en) Method of manufacturing transistor of semiconductor device
KR970024280A (en) Gate spacer formation method of semiconductor device
KR940001386A (en) Manufacturing Method of BiCMOS Device
KR970030499A (en) Manufacturing method of semiconductor device
KR960043173A (en) Highly Integrated Complementary Transistor (CMOSFET) Manufacturing Method
KR970024168A (en) A MOS transistor and a method of fabricating the same
KR920007225A (en) Manufacturing method of semiconductor device
KR970053040A (en) Manufacturing Method of CMOS Transistor
KR960039443A (en) Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof
KR970053080A (en) Manufacturing method of semiconductor device
KR950024331A (en) Semiconductor device manufacturing method
KR970024229A (en) Static random access memory device and manufacturing method thereof

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid