KR970053882A - Manufacturing method of BiCMOS transistor with simplified process - Google Patents

Manufacturing method of BiCMOS transistor with simplified process Download PDF

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KR970053882A
KR970053882A KR1019950069679A KR19950069679A KR970053882A KR 970053882 A KR970053882 A KR 970053882A KR 1019950069679 A KR1019950069679 A KR 1019950069679A KR 19950069679 A KR19950069679 A KR 19950069679A KR 970053882 A KR970053882 A KR 970053882A
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semiconductor substrate
oxide film
conductivity type
substrate
impurities
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KR1019950069679A
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Korean (ko)
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KR100363078B1 (en
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남주완
김산
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

바이 씨모오스(BiCMOS) 트랜지스터의 제조방법에 대해 기재되어 있다. 이는, 제1도전형의 반도체기판 전면에, 바이폴라 트랜지스터의 콜렉터를 형성하기 위한 제1도전형의 불순물을 이온주입하는 단계, 이온주입된 반도체 기판의 전면에 산화막을 형성하는 단계, 산화막을 패터닝하여 제1도전형의 웰(well)이 형성될 영역의 기판을 노출시키는 단계, 산화막을 이온주입 마스크로 사용하여 반도체 기판에 제1도전형의 불순물을 이온주입하는 단계, 산화막을 제거하는 단계, 반도체 기판상에 제2도전형의 웰이 형성될 영역의 기판을 노출시키는 마스크패턴을 형성하는 단계, 노출된 반도체 기판에 제2도전형의 불순물을 이온주입하는 단계 및 반도체 기판을 열처리함으로써, 주입된 불순물들을 활성화 및 확산시키는 단계를 포함하는 것을 특징으로 한다.A method for manufacturing a BiCMOS transistor is described. This is performed by ion implanting impurities of the first conductivity type for forming a collector of a bipolar transistor on the entire surface of the semiconductor substrate of the first conductivity type, forming an oxide film on the entire surface of the ion implanted semiconductor substrate, and patterning the oxide film. Exposing a substrate in a region where a well of a first conductivity type is to be formed, ion implanting impurities of a first conductivity type into a semiconductor substrate using an oxide film as an ion implantation mask, removing an oxide film, and a semiconductor Forming a mask pattern exposing the substrate of the region where the second conductivity type well is to be formed on the substrate, implanting impurities of the second conductivity type into the exposed semiconductor substrate, and heat treating the semiconductor substrate Activating and diffusing the impurities.

따라서, 종래에 비해 콜렉터 형성을 위한 사진공정을 생략할 수 있으므로, 공정을 단순화하고, 공정시간을 단축할 수 있으며, 제조원가를 절감할 수 있는 이점이 있다.Therefore, since the photo process for forming the collector can be omitted as compared with the related art, the process can be simplified, the process time can be shortened, and the manufacturing cost can be reduced.

Description

공정을 단순화한 바이 씨모오스(BiCMOS) 트랜지스터의 제조방법Method for Manufacturing BiCMOS Transistors Simplified Process

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도는 본 발명에 의한 BiCMOS 트랜지스터의 제조방법을 설명하기 위하여 공정수순에 따라 도시한 단면도들이다.5 is a cross-sectional view illustrating a method of manufacturing a BiCMOS transistor according to the present invention according to the process procedure.

Claims (4)

동일한 반도체 기판에 씨모스(CMOS) 트랜지스터와 바이폴라(Bipolar) 트랜지스터를 구비하는 집적회로 장치의 제조방법에 있어서, 제1도전형의 반도체기판 전면에, 바이폴라 트랜지스터의 콜렉터를 형성하기 위한 제1도전형의 불순물을 이온주입하는 단계; 상기 이온주입된 반도체 기판의 전면에 산화막을 형성하는 단계; 상기 산화막을 패터닝하여 제1도전형의 웰(well)이 형성될 영역의 기판을 노출시키는 단계; 상기 산화막을 이온주입 마스크로 사용하여 반도체 기판에 제1도전형의 불순물을 이온주입하는 단계; 상기 산화막을 제거하는 단계; 상기 반도체 기판상에 제2도전형의 웰이 형성될 영역의 기판을 노출시키는 마스크패턴을 형성하는 단계; 상기 노출된 반도체 기판에 제2도전형의 불순물을 이온주입하는 단계; 및 반도체 기판을 열처리함으로써, 상기 주입된 불순물들을 활성화 및 확산시키는 단계를 포함하는 것을 특징으로 하는 바이 씨모오스(BiCMOS) 트랜지스터의 제조방법.A method of manufacturing an integrated circuit device comprising a CMOS transistor and a bipolar transistor on the same semiconductor substrate, the first conductive type for forming a collector of a bipolar transistor on the entire surface of the first conductive semiconductor substrate. Ion implantation of impurities; Forming an oxide film on an entire surface of the ion implanted semiconductor substrate; Patterning the oxide film to expose a substrate in a region where a well of a first conductivity type is to be formed; Ion implanting impurities of a first conductivity type into a semiconductor substrate using the oxide film as an ion implantation mask; Removing the oxide film; Forming a mask pattern on the semiconductor substrate, the mask pattern exposing a substrate in a region where a second conductive type well is to be formed; Implanting impurities of a second conductivity type into the exposed semiconductor substrate; And activating and diffusing the implanted impurities by heat-treating a semiconductor substrate. 제1항에 있어서, 상기 제1도전형은 N형이고, 제2도전형은 P형인 것을 특징으로 하는 바이 씨모오스(BiCMOS) 트랜지스터의 제조방법.The method of claim 1, wherein the first conductive type is N type and the second conductive type is P type. 제1항에 있어서, 상기 산화막을 제거하는 단계 전에, 상기 산화막을 마스크로 사용하여 반도체기판을 산화시키는 단계 및 상기 산화시 형성된 산화막을 전면식각하는 단계를 더 구비하는 것을 특징으로 하는 바이 씨모오스(BiCMOS) 트랜지스터의 제조방법.The method of claim 1, further comprising oxidizing the semiconductor substrate using the oxide film as a mask and etching the entire surface of the oxide film formed during the oxidation before removing the oxide film. BiCMOS) transistor manufacturing method. 제1항에 있어서, 상기 제2도전형의 불순물을 이온주입하는 단계에서, 기판에이미 주입된 제1도전형의 불순물을 보상하고, 제2도전형의 웰이 형성될 정도의 충분한 도우즈로 주입하는 것을 특징으로 하는 바이 씨모오스(BiCMOS) 트랜지스터의 제조방법.The method of claim 1, wherein in the ion implantation of the second conductivity type impurities, the impurities of the first conductivity type already implanted in the substrate are compensated for and implanted with sufficient dose to form a well of the second conductivity type. A method of manufacturing a BiCMOS transistor, characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950069679A 1995-12-30 1995-12-30 Method for manufacturing process-simplified bicmos KR100363078B1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58225663A (en) * 1982-06-23 1983-12-27 Toshiba Corp Manufacture of semiconductor device
JPS6394677A (en) * 1986-10-09 1988-04-25 Pioneer Electronic Corp Manufacture of semiconductor element
KR910008945B1 (en) * 1988-04-21 1991-10-26 삼성전자 주식회사 Method of manufacturing bi-cmos semiconductor device
JPH01310536A (en) * 1988-06-08 1989-12-14 Sharp Corp Manufacture of semiconductor device
KR940004257B1 (en) * 1991-01-18 1994-05-19 금성일렉트론 주식회사 Manufacturing method of bipolar transistor
US5411900A (en) * 1993-03-05 1995-05-02 Deutsche Itt Industries, Gmbh Method of fabricating a monolithic integrated circuit with at least one CMOS field-effect transistor and one NPN bipolar transistor

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