KR970053632A - Stacked Area Array Package and Manufacturing Method Thereof - Google Patents

Stacked Area Array Package and Manufacturing Method Thereof Download PDF

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Publication number
KR970053632A
KR970053632A KR1019950050642A KR19950050642A KR970053632A KR 970053632 A KR970053632 A KR 970053632A KR 1019950050642 A KR1019950050642 A KR 1019950050642A KR 19950050642 A KR19950050642 A KR 19950050642A KR 970053632 A KR970053632 A KR 970053632A
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KR
South Korea
Prior art keywords
package
array package
area array
substrate
area
Prior art date
Application number
KR1019950050642A
Other languages
Korean (ko)
Inventor
송치중
김진성
Original Assignee
문정환
Lg 반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, Lg 반도체주식회사 filed Critical 문정환
Priority to KR1019950050642A priority Critical patent/KR970053632A/en
Publication of KR970053632A publication Critical patent/KR970053632A/en

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Abstract

본 발명은 적층형 에리어 어레이 패키지 및 그 제조방법에 관한 것으로, 종래의 스테커 칩 패키지는 인너리드와 아웃리드를 고난도의 레이저 접합을 이용하여 접합하기 때문에 생산이 어려울뿐만 아니라, 생산성 향상에 한계가 있는 문제점이 등이 있었던 바, 본 발명의 적층형 에리어 어레이 패키지는 전도성 볼(24)과 솔더볼(25')을 얼라인하고 부분 융착하여 순간적으로 접합함으로써 제조시간의 절감에 따른 생산성의 향상효과가 있고, 종래의 와이어(15)를 배제하고 전기전인 연결이 이루어짐에 따라 패키지가 경박단소화 되는 효과가 있다.The present invention relates to a stacked area array package and a method of manufacturing the same. In the conventional stacker chip package, since the inner lead and the outer lead are bonded by using a high level laser bonding, not only the production is difficult but also the productivity is limited. Since there are problems, the laminated area array package of the present invention has an effect of improving productivity by reducing manufacturing time by aligning and partially bonding the conductive balls 24 and the solder balls 25 'and temporarily bonding them. Except for the conventional wire 15 has the effect of making the package light and short as the electric connection is made.

Description

적층형 에리어 어레이 패키지 및 그 제조방법Stacked Area Array Package and Manufacturing Method Thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명 에리어 어레이 패키지의 구조를 보인 종단면도이다.2 is a longitudinal sectional view showing the structure of the area array package of the present invention.

Claims (4)

상, 하 방향으로 내설된 수개의 패턴이 구비된 서브스트레이트의 중앙에 안착흠이 설치되고, 그 안착홈의 상부에 상기 패턴과 각각 연결된 수개의 전도성 볼을 매개로 반도체 칩이 설치되며, 상기 반도체 칩이 설치된 안착흠이 내부에 에폭시로 몰딩부가 형성되고, 상기 서브스트레이트의 단차부 상면에 상기 패턴과 연결되도록 전도성 볼이 설치되며, 상기 서브스트레이트의 하면에 상기 패턴과 연결되도록 솔더볼이 부착되어서 에리어 어레이 패키지가 구성되고, 이러한 에리어 패키지의 전도성볼에 다른 에리어 어레이 패키지의 서브스트레이트 하면에 부착된 솔더볼을 접합하여 적층한 것을 특징으로 하는 적층형 에리어 어레이 패키지.The mounting flaw is installed in the center of the substrate provided with several patterns in the up and down directions, and the semiconductor chip is installed in the upper part of the mounting groove via several conductive balls connected to the pattern, respectively. The chipped mounting defect is formed with an epoxy molding portion therein, a conductive ball is installed on the upper surface of the stepped portion of the substrate to be connected to the pattern, and a solder ball is attached to the lower surface of the substrate so as to be connected to the pattern. An array package comprising a stacked area array package comprising a solder ball attached to a lower surface of a substrate of another area array package to a conductive ball of the area package. 제1항에 있어서, 상기 적층형 에리어 패키지는 에리어 패키지를 2개 이상 적층한 것을 특징으로 하는 적층형 에리어 어레이 패키지.2. The stacked area array package of claim 1, wherein the stacked area package is formed by stacking two or more area packages. 제1항에 있어서, 상기 에리어 어레이 패키지의 서브스트레이트에 형성된 안착흠의 하면으로는 패키지 작동시 열을 방출하기 위한 수개의 열방출공이 형성된 것을 특징으로 하는 적층형 에리어 어레이 패키지.The stacked area array package of claim 1, wherein a plurality of heat dissipation holes are formed on a lower surface of the mounting recess formed in the substrate of the area array package to release heat during the operation of the package. 에리어 어레이 패키지의 전도성 볼에 다른 에리어 패키지의 서브스트레이트 하면에 부착된 솔더볼을 정렬하는 정렬공정을 수행하는 단계와, 상기 전도성 볼과 솔더볼을 부분융착하여 접합하는 접합공정을 수행하는 단계의 순서로 제조되는 것을 특징으로 하는 적층형 에리어 어레이 패키지의 제조방법.The manufacturing process is performed by aligning the solder balls attached to the substrate lower surface of the other area package to the conductive balls of the area array package, and performing a bonding process of partially fusion bonding the conductive balls and the solder balls. Method of manufacturing a stacked area array package, characterized in that the. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950050642A 1995-12-15 1995-12-15 Stacked Area Array Package and Manufacturing Method Thereof KR970053632A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950050642A KR970053632A (en) 1995-12-15 1995-12-15 Stacked Area Array Package and Manufacturing Method Thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950050642A KR970053632A (en) 1995-12-15 1995-12-15 Stacked Area Array Package and Manufacturing Method Thereof

Publications (1)

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KR970053632A true KR970053632A (en) 1997-07-31

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KR1019950050642A KR970053632A (en) 1995-12-15 1995-12-15 Stacked Area Array Package and Manufacturing Method Thereof

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990040758A (en) * 1997-11-19 1999-06-05 김영환 Vigie package and its manufacturing method
KR100424188B1 (en) * 1998-09-21 2004-05-17 주식회사 하이닉스반도체 Chip size stack package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990040758A (en) * 1997-11-19 1999-06-05 김영환 Vigie package and its manufacturing method
KR100424188B1 (en) * 1998-09-21 2004-05-17 주식회사 하이닉스반도체 Chip size stack package

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