KR970053632A - Stacked Area Array Package and Manufacturing Method Thereof - Google Patents
Stacked Area Array Package and Manufacturing Method Thereof Download PDFInfo
- Publication number
- KR970053632A KR970053632A KR1019950050642A KR19950050642A KR970053632A KR 970053632 A KR970053632 A KR 970053632A KR 1019950050642 A KR1019950050642 A KR 1019950050642A KR 19950050642 A KR19950050642 A KR 19950050642A KR 970053632 A KR970053632 A KR 970053632A
- Authority
- KR
- South Korea
- Prior art keywords
- package
- array package
- area array
- substrate
- area
- Prior art date
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- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
본 발명은 적층형 에리어 어레이 패키지 및 그 제조방법에 관한 것으로, 종래의 스테커 칩 패키지는 인너리드와 아웃리드를 고난도의 레이저 접합을 이용하여 접합하기 때문에 생산이 어려울뿐만 아니라, 생산성 향상에 한계가 있는 문제점이 등이 있었던 바, 본 발명의 적층형 에리어 어레이 패키지는 전도성 볼(24)과 솔더볼(25')을 얼라인하고 부분 융착하여 순간적으로 접합함으로써 제조시간의 절감에 따른 생산성의 향상효과가 있고, 종래의 와이어(15)를 배제하고 전기전인 연결이 이루어짐에 따라 패키지가 경박단소화 되는 효과가 있다.The present invention relates to a stacked area array package and a method of manufacturing the same. In the conventional stacker chip package, since the inner lead and the outer lead are bonded by using a high level laser bonding, not only the production is difficult but also the productivity is limited. Since there are problems, the laminated area array package of the present invention has an effect of improving productivity by reducing manufacturing time by aligning and partially bonding the conductive balls 24 and the solder balls 25 'and temporarily bonding them. Except for the conventional wire 15 has the effect of making the package light and short as the electric connection is made.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명 에리어 어레이 패키지의 구조를 보인 종단면도이다.2 is a longitudinal sectional view showing the structure of the area array package of the present invention.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950050642A KR970053632A (en) | 1995-12-15 | 1995-12-15 | Stacked Area Array Package and Manufacturing Method Thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950050642A KR970053632A (en) | 1995-12-15 | 1995-12-15 | Stacked Area Array Package and Manufacturing Method Thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970053632A true KR970053632A (en) | 1997-07-31 |
Family
ID=66594412
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950050642A KR970053632A (en) | 1995-12-15 | 1995-12-15 | Stacked Area Array Package and Manufacturing Method Thereof |
Country Status (1)
Country | Link |
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KR (1) | KR970053632A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990040758A (en) * | 1997-11-19 | 1999-06-05 | 김영환 | Vigie package and its manufacturing method |
KR100424188B1 (en) * | 1998-09-21 | 2004-05-17 | 주식회사 하이닉스반도체 | Chip size stack package |
-
1995
- 1995-12-15 KR KR1019950050642A patent/KR970053632A/en not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990040758A (en) * | 1997-11-19 | 1999-06-05 | 김영환 | Vigie package and its manufacturing method |
KR100424188B1 (en) * | 1998-09-21 | 2004-05-17 | 주식회사 하이닉스반도체 | Chip size stack package |
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Legal Events
Date | Code | Title | Description |
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A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |