KR970053592A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
KR970053592A
KR970053592A KR1019950055132A KR19950055132A KR970053592A KR 970053592 A KR970053592 A KR 970053592A KR 1019950055132 A KR1019950055132 A KR 1019950055132A KR 19950055132 A KR19950055132 A KR 19950055132A KR 970053592 A KR970053592 A KR 970053592A
Authority
KR
South Korea
Prior art keywords
trench
region
film
forming
field oxide
Prior art date
Application number
KR1019950055132A
Other languages
Korean (ko)
Other versions
KR100208434B1 (en
Inventor
신윤섭
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950055132A priority Critical patent/KR100208434B1/en
Publication of KR970053592A publication Critical patent/KR970053592A/en
Application granted granted Critical
Publication of KR100208434B1 publication Critical patent/KR100208434B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 반도체 소자 및 그 제조방법이 개시된다. 웨이퍼의 다이 분리 공정시 불순물 또는 습기가 프로덕트 다이상의 소자 형성 영역으로 침투하는 것을 완전히 방지하기 위해 다이 외각 라인과 스크라이브 라인 사이에 트랜치를 형성시킨다.The present invention discloses a semiconductor device and a method of manufacturing the same. A trench is formed between the die outer line and the scribe line to completely prevent impurities or moisture from penetrating into the device formation region on the product die during the die separation process of the wafer.

Description

반도체 소자 및 그 제조 방법Semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명의 제1실시에 따른 반도체 소자 제조방법을 설명하기 위한 평면도이다.4 is a plan view illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

Claims (6)

반도체 소자에 있어서, 다이 외각 라인과 스크라이브 라인 사이에 트랜치를 영역이 형성된 것을 특징으로 하는 반도체 소자.A semiconductor device, comprising: a trench formed between a die outer line and a scribe line; 제1항에 있어서, 상기 트랜치 영역은 실리콘 기판상에 서로 이격 되도록 형성되는 필드 산화막들과, 상기 필드 산화막들 사이의 실리콘 기판상에 형성되는 트랜치와, 상기 필드 산화막들 및 트랜치의 표면에 순차로 형성되는 절연막 및 BPSG층과, 상기 BPSG층 상부에 형성되는 보호막으로 구성되는 것을 특징으로 하는 반도체 소자.2. The trench region of claim 1, wherein the trench regions are formed on the silicon substrate so as to be spaced apart from each other, a trench formed on the silicon substrate between the field oxide layers, and a surface of the field oxide layers and the trench. And an insulating film to be formed and a BPSG layer and a protective film formed on the BPSG layer. 반도체 소자 제조 방법에 있어서, 실리콘 기판상에 필드 산화막을 형성하여 트랜치 영역과 가드링 영역을 확정하고, 트랜치 영역의 필드 산화막 사이에 제1트랜치를 형성하는 단계와, 상기 가드링 영역의 필드 산화막 사이의 실리콘 기판상에 불순물 이온을 주입하여 접합영역을 형성하고 그 상부에 산화막을 형성한 다음 그 상부에 도전체를 증착하고 도전체를 패터닝 하여 가드링 영역에 도전층을 형성하는 단계와, 상기 도전층을 형성한 전체 구조 상부에 절연막 및 BPSG막을 순차적으로 증착하는 단계와, 상기 절연막 및 BPSG막의 일부를 식각하여 상기 접합영역 및 도전층의 일부가 노출되도록 콘택홀을 형성하는 단계와, 상기 콘택홀이 매립되도록 금속을 증착한 다음 패터닝하여 경사가 큰 금속층을 형성하고 전체 구조 상부에 보호막을 증착하는 단계와, 트랜치 영역의 보호막을 패터닝 하여 제2트랜치를 형성하는 단계로 이루어진 것을 특징으로 하는 반도체 소자 제조 방법.A method of manufacturing a semiconductor device, comprising: forming a field oxide film on a silicon substrate to determine a trench region and a guard ring region, and forming a first trench between the field oxide films of the trench regions, and between the field oxide films of the guard ring regions. Implanting impurity ions on the silicon substrate of the semiconductor substrate to form a junction region, forming an oxide film thereon, depositing a conductor thereon, and patterning the conductor to form a conductive layer in the guard ring region; Sequentially depositing an insulating film and a BPSG film over the entire layered structure, etching a portion of the insulating film and the BPSG film, and forming a contact hole to expose a portion of the junction region and the conductive layer, and the contact hole Metal is deposited to be buried and then patterned to form a highly inclined metal layer and a protective film is deposited over the entire structure. And a semiconductor device manufacturing method characterized by patterning the protective layer of the trench region consisting of forming a second trench. 제3항에 있어서, 상기 제1트랜치는 소자 분리 마스크를 사용한 식각 공정에 의해 형성되는 것을 특징으로 하는 반도체 소자 제조 방법.The method of claim 3, wherein the first trench is formed by an etching process using an element isolation mask. 제3항에 있어서, 상기 제2트랜치는 패드 마스크를 사용한 식각 공정에 의해 형성되는 것을 특징으로 하는 반도체 소자 제조 방법.The method of claim 3, wherein the second trench is formed by an etching process using a pad mask. 제3항에 있어서, 상기 도전층은 폴리 마스크를 이용한 식각 공정에 의해 형성되는 것을 특징으로 하는 반도체 소자 제조 방법.The method of claim 3, wherein the conductive layer is formed by an etching process using a poly mask. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950055132A 1995-12-23 1995-12-23 Semiconductor device and manufacture thereof KR100208434B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950055132A KR100208434B1 (en) 1995-12-23 1995-12-23 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950055132A KR100208434B1 (en) 1995-12-23 1995-12-23 Semiconductor device and manufacture thereof

Publications (2)

Publication Number Publication Date
KR970053592A true KR970053592A (en) 1997-07-31
KR100208434B1 KR100208434B1 (en) 1999-07-15

Family

ID=19443600

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950055132A KR100208434B1 (en) 1995-12-23 1995-12-23 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
KR (1) KR100208434B1 (en)

Also Published As

Publication number Publication date
KR100208434B1 (en) 1999-07-15

Similar Documents

Publication Publication Date Title
KR890003038A (en) Semiconductor manufacturing process with pedestal structure
JPS55163860A (en) Manufacture of semiconductor device
KR970013074A (en) Planarization method of semiconductor device and device isolation method using same
KR900019155A (en) Contact Formation Method Using Etch Barrier
KR940012650A (en) Contact manufacturing method of semiconductor device
GB1453270A (en) Field effect devices
JPH06163578A (en) Method for forming contact hole
EP0877420A3 (en) Method of forming a polysilicon buried contact and a structure thereof
KR970053592A (en) Semiconductor device and manufacturing method thereof
KR980006262A (en) CMOS semiconductor structure and method of manufacturing the structure
JPS5764927A (en) Manufacture of semiconductor device
JP2695812B2 (en) Semiconductor device
JPH0346502Y2 (en)
KR870001655A (en) Manufacturing Method of Semiconductor Device
KR970053546A (en) Metal wiring formation method of semiconductor device
KR100357174B1 (en) Method for fabricating capacitor of semiconductor device
KR100267217B1 (en) Method for forming guard ring of semiconductor device
KR900017141A (en) Method of forming buried contacts during semiconductor device manufacturing
KR970053470A (en) Device Separation Method of Semiconductor Device
KR970052364A (en) Contact Forming Method of Semiconductor Device
KR880010473A (en) Manufacturing Method of Semiconductor Device
KR980005474A (en) Semiconductor device manufacturing method
KR960030414A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960012324A (en) Gate electrode contact of semiconductor device and manufacturing method thereof
KR960039397A (en) Mask ROM Cell Manufacturing Method

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070321

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee