KR970053561A - Via hole formation method of semiconductor device - Google Patents
Via hole formation method of semiconductor device Download PDFInfo
- Publication number
- KR970053561A KR970053561A KR1019950065860A KR19950065860A KR970053561A KR 970053561 A KR970053561 A KR 970053561A KR 1019950065860 A KR1019950065860 A KR 1019950065860A KR 19950065860 A KR19950065860 A KR 19950065860A KR 970053561 A KR970053561 A KR 970053561A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- insulating film
- film
- etching
- insulating layer
- Prior art date
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 다층 배선 구조를 갖는 반도체 장치의 층간 절연막에 비아홀을 형성하는 방법에 관한 것으로서, 다층 배선 구조를 갖는 반도체 장치의 층간 절연막을 형성함에 있어서, 하부 메탈의 상부에 제1절연막을 형성하는 단계; 상기 제1절연막 상에 실리콘질화막을 형성하는 단계; 상기 실리콘질화막 상에 제2잘연막을 형성하는 단계; 포토레지스트를 이용한 에치백 공정으로 상기 제2절연막을 평탄화시키는 단계; 상기 제2절연막상에 비아홀 형성을 위한 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 식각마스크로 사용하여 제2절연막을 선택적으로 습식식각하는 단계; 및, 상기 제2절연막의 식각 부분을 통하여 실리콘질화막 및 제1절연막을 건식 식각하는 단계를 포함하여 이루어진 것으로, 건식 식각하는 제1절연막의 두께가 비아홀 형성 지점에 관계없이 일정하여 제1절연막의 과도 식각을 방지할 수 있으므로 하부 메탈의 손상을 최소화 할 수 있으며, 하부 메탈 간의 단차가 높은 곳에서의 제1절연막 두께를 낮게 형성함으로써 상부 메탈 형성 공정에서의 스텝커버리지를 향상시킬 수 있는 것이다.The present invention relates to a method for forming a via hole in an interlayer insulating film of a semiconductor device having a multi-layered wiring structure, the method comprising: forming a first insulating film on an upper portion of a lower metal in forming an interlayer insulating film of a semiconductor device having a multi-layered wiring structure ; Forming a silicon nitride film on the first insulating film; Forming a second well film on the silicon nitride film; Planarizing the second insulating layer by an etch back process using a photoresist; Forming a photoresist pattern for forming a via hole on the second insulating layer; Selectively wet etching a second insulating layer using the photoresist pattern as an etching mask; And dry etching the silicon nitride film and the first insulating film through the etching portion of the second insulating film, wherein the thickness of the first insulating film to be dry etched is constant regardless of the via hole formation point. Since the etching can be prevented, damage to the lower metal can be minimized, and the step coverage in the upper metal forming process can be improved by lowering the thickness of the first insulating layer at a high level between the lower metals.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2도는 본 발명에 따른 반도체 장치의 비아홀 형성 공정도이다.2 is a process diagram for forming via holes in a semiconductor device according to the present invention.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950065860A KR970053561A (en) | 1995-12-29 | 1995-12-29 | Via hole formation method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950065860A KR970053561A (en) | 1995-12-29 | 1995-12-29 | Via hole formation method of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970053561A true KR970053561A (en) | 1997-07-31 |
Family
ID=66622772
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950065860A KR970053561A (en) | 1995-12-29 | 1995-12-29 | Via hole formation method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970053561A (en) |
-
1995
- 1995-12-29 KR KR1019950065860A patent/KR970053561A/en not_active Application Discontinuation
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WITN | Withdrawal due to no request for examination |