KR970053549A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR970053549A
KR970053549A KR1019950061998A KR19950061998A KR970053549A KR 970053549 A KR970053549 A KR 970053549A KR 1019950061998 A KR1019950061998 A KR 1019950061998A KR 19950061998 A KR19950061998 A KR 19950061998A KR 970053549 A KR970053549 A KR 970053549A
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KR
South Korea
Prior art keywords
depositing
metal
barrier metal
silicide
titanium
Prior art date
Application number
KR1019950061998A
Other languages
Korean (ko)
Inventor
김응수
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950061998A priority Critical patent/KR970053549A/en
Publication of KR970053549A publication Critical patent/KR970053549A/en

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Abstract

본 발명은 기존의 설비와 공정을 이용하여 콘택이나 비아홀 충입방법을 통하여 단차 피복을 향상시킨 반도체 장치의 제조 방법에 관한 것이다. 기판 위에 산화락을 형성한 후 금속 배선층 컨택홀이 형성되도록 패터닝하는 단계, 상기 금속 배선층 콘택홀의 상부에 제1장벽 금속을 증착하는 단계, 실리사이드 또는 외인성 폴리 실리콘을 증착하는 단계, 상기 산화막 위에 상기 제1장벽 금속까지 건식 식각하는 단계, 제2장벽 금속층을 증착하고 금속을 증착한 후 패터닝하는 단계를 포함하여 이루어진다.The present invention relates to a method of manufacturing a semiconductor device having improved step coverage by using a contact or via hole filling method using existing equipment and processes. Forming an oxide layer on the substrate and patterning a metal wiring layer contact hole to be formed; depositing a first barrier metal on the metal wiring layer contact hole; depositing a silicide or exogenous polysilicon; Dry etching to the first barrier metal, and depositing the second barrier metal layer, depositing the metal and then patterning the metal.

Description

반도체 장치의 제조 방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 (가)-(나)는 본 발명의 실시예에 따른 콘택홀에서의 플러그 형성을 나타낸 단면도이다.2 is a cross-sectional view illustrating the plug formation in the contact hole according to the embodiment of the present invention.

Claims (6)

기판 위에 산화막을 형성한 후 금속 배선층 컨택홀이 형성되도록 패터닝하는 단계, 상기 금속 배선층 콘택홀의 상부에 제1장벽 금속을 증착하는 단계, 실리사이드 또는 외인성 폴리 실리콘을 증착하는 단계, 상기 산화막 위에 상기 제1장벽 금속까지 건식 식각하는 단계, 제2장벽 금속층을 증착하고 금속을 증착한 후 패터닝하는 단계를 포함하여 이루어지는 반도체 장치의 제조 방법.Forming an oxide film on the substrate and patterning a metal wiring layer contact hole to be formed; depositing a first barrier metal on the metal wiring layer contact hole; depositing a silicide or exogenous polysilicon; Dry etching to the barrier metal, depositing the second barrier metal layer, depositing the metal, and then patterning the semiconductor device. 제1항에서, 상기 제1장벽 금속은 티타늄, 티타늄 질화물/티타늄, 티타늄 텅스텐중 어느 하나로 형성하는 반도체 장치의 제조 방법.The method of claim 1, wherein the first barrier metal is formed of any one of titanium, titanium nitride / titanium, and titanium tungsten. 제1항에서, 상기 실리 사이드는 텅스텐 실리 사이드, 티타늄 실리 사이드, 니켈실리 사이드중 어느 하나로 형성하는 반도체 장치의 제조 방법.The method of claim 1, wherein the silicide is formed of any one of tungsten silicide, titanium silicide, and nickel silicide. 제1항에서, 상기 외인성 반도체막은 폴리 실리콘에 포클이나 고농도 이온주입하여 형성하는 반도체 장치의 제조 방법.The method of manufacturing a semiconductor device according to claim 1, wherein the exogenous semiconductor film is formed by injecting polycone or high concentration ions into polysilicon. 제1항에서, 상기 건식 식각은 스퍼터 에치나 리액티브 에치, 씨엠피중 어느 하나로 식각하는 반도체 장치의 제조 방법.The method of claim 1, wherein the dry etching is performed using any one of sputter etching, reactive etching, and CMP. 제2항에서, 상기 제2장벽 금속은 TiN 또는 TiW등으로 형성하는 반도체 장치의 제조 방법.The method of claim 2, wherein the second barrier metal is formed of TiN, TiW, or the like. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950061998A 1995-12-28 1995-12-28 Manufacturing Method of Semiconductor Device KR970053549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950061998A KR970053549A (en) 1995-12-28 1995-12-28 Manufacturing Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950061998A KR970053549A (en) 1995-12-28 1995-12-28 Manufacturing Method of Semiconductor Device

Publications (1)

Publication Number Publication Date
KR970053549A true KR970053549A (en) 1997-07-31

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950061998A KR970053549A (en) 1995-12-28 1995-12-28 Manufacturing Method of Semiconductor Device

Country Status (1)

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KR (1) KR970053549A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100390042B1 (en) * 2001-06-27 2003-07-04 주식회사 하이닉스반도체 Method for forming bit line of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100390042B1 (en) * 2001-06-27 2003-07-04 주식회사 하이닉스반도체 Method for forming bit line of semiconductor device

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