KR970053515A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR970053515A
KR970053515A KR1019950046998A KR19950046998A KR970053515A KR 970053515 A KR970053515 A KR 970053515A KR 1019950046998 A KR1019950046998 A KR 1019950046998A KR 19950046998 A KR19950046998 A KR 19950046998A KR 970053515 A KR970053515 A KR 970053515A
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KR
South Korea
Prior art keywords
forming
peripheral circuit
semiconductor substrate
insulating film
cell portion
Prior art date
Application number
KR1019950046998A
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Korean (ko)
Inventor
최양규
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950046998A priority Critical patent/KR970053515A/en
Publication of KR970053515A publication Critical patent/KR970053515A/en

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Abstract

본 발명은 반도체소자의 제조방법에 관한 것으로, 반도체기판 상부에 소자분리절연막을 형성하고 이를 마스크로하여 상기 반도체기판 셀부 또는 주변회로부에 각각 불순물영역을 형성한 다음, 전체표면상부를 평탄화시키는 하부절연층으로 형성하고 상기 셀부의 불순물영역에 접속되는 저장전극용 다결정실리콘막을 일정두께 형성한 다음, 저장전극마스크를 이용한 식각공정으로 저장전극용 다결정실리콘막패턴을 형성하고 유전체막과 플레이크전극을 순차적으로 형성한 다음, 셀부와 주변회로부가 전기적으로 격리되도록 상기 플레이트전극을 식각하고 상부절연층을 형성하는 것과 같이 셀부와 주변회로부 각각에 전기적으로 단락된 캐패시터를 형성함으로써 단차를 없애 후속공정을 용하게 실시할 수 있어 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 기술이다.The present invention relates to a method for fabricating a semiconductor device, comprising: forming a device isolation insulating film on a semiconductor substrate and forming an impurity region in the semiconductor substrate cell portion or a peripheral circuit portion, respectively, as a mask, and then lower insulating to planarize the entire upper surface thereof. After forming a layer and forming a predetermined thickness of the storage electrode polysilicon film connected to the impurity region of the cell portion, a polysilicon film pattern for the storage electrode is formed by an etching process using the storage electrode mask, and the dielectric film and the flake electrode are sequentially formed. After the formation, the plate electrode is etched so that the cell portion and the peripheral circuit portion are electrically isolated, and an electrically shorted capacitor is formed in each of the cell portion and the peripheral circuit portion such as to form an upper insulating layer, thereby eliminating the step to facilitate the subsequent process. Improves the characteristics and reliability of semiconductor devices A technique that can kill.

Description

반도체소자 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명의 실시예에 따른 반도체소자 제조방법을 도시한 단면도.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Claims (3)

반도체기판 상부에 소자분리절연막을 형성하는 공정과, 상기 소자분리절연막을 마스크로 하여 반도체기판에 불순물을 이온주입하여 상기 반도체기판의 셀부와 주변회로부에 각각 불순물영역을 형성하는 공정과, 전체표면상부에 하부절연층을 형성하는 공정과, 상기 셀부의 불순물영역에 접속되는 도전체를 전체표면상부에 형성하는 공정과, 저장전극마스크를 이용한 식각공정으로 저장전극을 형성하는 공정과, 전체표면상부에 유전체막과 플레이트전극을 형성하되, 상기 플레이트전극은 셀부와 주변회로가 각각 격리되어 형성되는 공정과, 전체표면상부에 상부절연층을 형성하는 공정과, 상기 주변회로부터 불순물영역이 노출되는 콘택홀을 형성하는 공정과, 상기 콘택홀의 측벽에 절연막 스페이서를 형성하는 공정과, 상기 콘택홀이 매립되는 금속배선을 형성하는 공정을 포함하는 반도체소자 제조방법.Forming a device isolation insulating film on the semiconductor substrate; forming an impurity region in each of the cell portion and the peripheral circuit portion of the semiconductor substrate by implanting impurities into the semiconductor substrate using the device isolation insulating film as a mask; Forming a lower insulating layer on the upper surface, forming a conductor connected to the impurity region of the cell portion over the entire surface, forming a storage electrode in an etching process using a storage electrode mask, Forming a dielectric film and a plate electrode, wherein the plate electrode is formed by separating cell portions and peripheral circuits separately; forming an upper insulating layer over the entire surface; and contact holes exposing impurity regions from the peripheral circuit. Forming an insulating film spacer; forming an insulating film spacer on the sidewalls of the contact hole; Method of manufacturing a semiconductor device including a step of forming a wiring. 제1항에 있어서, 상기 절연막 스페이서는 산화막이나 질화막으로 형성되는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the insulating film spacer is formed of an oxide film or a nitride film. 제1항에 있어서, 상기 절연막 스페이서는 LPCVD 또는 PECVD 방법으로 형성되는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the insulating layer spacer is formed by LPCVD or PECVD. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950046998A 1995-12-06 1995-12-06 Semiconductor device manufacturing method KR970053515A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950046998A KR970053515A (en) 1995-12-06 1995-12-06 Semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950046998A KR970053515A (en) 1995-12-06 1995-12-06 Semiconductor device manufacturing method

Publications (1)

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KR970053515A true KR970053515A (en) 1997-07-31

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KR1019950046998A KR970053515A (en) 1995-12-06 1995-12-06 Semiconductor device manufacturing method

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KR (1) KR970053515A (en)

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