KR970053507A - Multilayer wiring structure of semiconductor device and manufacturing method thereof - Google Patents

Multilayer wiring structure of semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
KR970053507A
KR970053507A KR1019950046087A KR19950046087A KR970053507A KR 970053507 A KR970053507 A KR 970053507A KR 1019950046087 A KR1019950046087 A KR 1019950046087A KR 19950046087 A KR19950046087 A KR 19950046087A KR 970053507 A KR970053507 A KR 970053507A
Authority
KR
South Korea
Prior art keywords
insulating film
metal
forming
metal layer
semiconductor device
Prior art date
Application number
KR1019950046087A
Other languages
Korean (ko)
Other versions
KR0179707B1 (en
Inventor
황준
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950046087A priority Critical patent/KR0179707B1/en
Publication of KR970053507A publication Critical patent/KR970053507A/en
Application granted granted Critical
Publication of KR0179707B1 publication Critical patent/KR0179707B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 장치의 다층 배선구조 제조방법에 관한 것으로, 인접한 금속라인간의 간격을 노광기의 해상력 한계 이하로 최소로 유지할 수 있도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multi-layered wiring structure of a semiconductor device, wherein the spacing between adjacent metal lines can be kept to a minimum below the resolution limit of the exposure machine.

본 발명은 반도체기판상에 층간절연막을 형성하는 단계와; 상기 층간절연막을 선택적으로 식각하여 복수 개의 콘택트을 형성하는 단계; 기판 전면에 제1금속층을 형성하는 단계; 상기 제1금속층상에 제1절연막을 형성하는 단계; 상기 제1절연막과 제1금속층을 소정패턴으로 패터닝하여 제1금속배선을 형성하는 단계; 상기 제1금속배선의 노출된 표면에만 제2절연막을 형성하는 단계; 기판 전면에 제2금속층을 형성하는 단계; 및 상기 제2금속층을 상기 제1금속배선 상부의 제1절연막이 노출되도록 화학적 기계 연마하여 제2금속배선을 형성하는 단계로 이루어지는 반도체 장치의 다층 배선구조의 제조방법을 제공한다.The present invention comprises the steps of forming an interlayer insulating film on a semiconductor substrate; Selectively etching the interlayer insulating film to form a plurality of contacts; Forming a first metal layer on the entire surface of the substrate; Forming a first insulating film on the first metal layer; Patterning the first insulating layer and the first metal layer in a predetermined pattern to form a first metal wiring; Forming a second insulating film only on the exposed surface of the first metal wiring; Forming a second metal layer on the entire surface of the substrate; And chemically mechanically polishing the second metal layer to expose the first insulating layer on the first metal wire, thereby forming a second metal wire.

Description

반도체 장치의 다층 배선구조 및 그 제조방법Multilayer wiring structure of semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 반도체 장치의 다층 배선구조 형성방법을 도시한 공정순서도.2 is a process flowchart showing a method for forming a multilayer wiring structure of a semiconductor device according to the present invention.

Claims (10)

반도체기판과; 상기 반도체기판상에 형성된 복수 개의 콘택홀을 갖춘 층간절연막; 상기 복수 개의 콘택홀 상에 형성되어 콘택홀을 통해 기판에 접속되되, 콘택홀을 하나씩 건너뛰어 형성되는 복수 개의 제1금속배선; 상기 제1금속배선 전표면에 형성된 절연막; 및 상기 제1금속배선 사이사이에 상기 콘택홀을 통해 기판에 접속되는 복수 개의 제2금속배선으로 구성되는 것을 특징으로 하는 반도체 장치의 다층 배선구조.A semiconductor substrate; An interlayer insulating film having a plurality of contact holes formed on the semiconductor substrate; A plurality of first metal wires formed on the plurality of contact holes and connected to the substrate through the contact holes, wherein the plurality of first metal wires are formed by skipping the contact holes one by one; An insulating film formed on the entire surface of the first metal wiring; And a plurality of second metal wirings connected to the substrate through the contact hole between the first metal wirings. 제1항에 있어서, 상기 절연막은 Al2O3막임을 특징으로 하는 반도체 장치의 다층 배선구조.The multilayer wiring structure of a semiconductor device according to claim 1, wherein said insulating film is an Al 2 O 3 film. 반도체기판상에 층간절연막을 형성하는 단계와; 상기 층간절연막을 선택적으로 식각하여 복수 개의 콘택홀을 형성하는 단계; 기판 전면에 제1금속층을 형성하는 단계; 상기 제1금속층상에 제1절연막을 형성하는 단계; 상기 제1절연막과 제1금속층을 소정패턴으로 패터닝하여 제1금속배선을 형성하는 단계; 상기 제1금속배선의 노출된 표면에만 제2절연막을 형성하는 단계; 기판 전면에 제2금속층을 형성하는 단계; 및 상기 제2금속층을 상기 제1금속배선 상부의 제1절연막이 노출되도록 화학적 기계 연마하여 제2금속배선을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 장치의 다층 배선구조의 제조방법.Forming an interlayer insulating film on the semiconductor substrate; Selectively etching the interlayer insulating film to form a plurality of contact holes; Forming a first metal layer on the entire surface of the substrate; Forming a first insulating film on the first metal layer; Patterning the first insulating layer and the first metal layer in a predetermined pattern to form a first metal wiring; Forming a second insulating film only on the exposed surface of the first metal wiring; Forming a second metal layer on the entire surface of the substrate; And chemically mechanically polishing the second metal layer to expose the first insulating layer on the first metal wiring to form a second metal wiring. 제3항에 있어서, 상기 제1금속층 및 제2금속층은 Al으로 형성하는 것을 특징으로 하는 반도체 장치의 다층 배선구조의 제조방법.The method of manufacturing a multilayer wiring structure of a semiconductor device according to claim 3, wherein said first metal layer and said second metal layer are formed of Al. 제3항에 있어서, 상기 제1절연막 및 제2절연막은 Al2O3로 형성하는 것을 특징으로 하는 반도체 장치의 다층 배선구조의 제조방법.The method of manufacturing a multilayer wiring structure of a semiconductor device according to claim 3, wherein said first insulating film and said second insulating film are formed of Al 2 O 3 . 제3항에 있어서, 상기 제1절연막은 상기 제1금속층이 형성된 기판을 뜨거운 순수에 린스함으로써 성장시키는 자연산화막으로 형성하는 것을 특징으로 하는 반도체 장치의 다층 배선구조의 제조방법.The method of manufacturing a multilayer wiring structure of a semiconductor device according to claim 3, wherein said first insulating film is formed of a natural oxide film grown by rinsing a substrate on which said first metal layer is formed with hot pure water. 제3항에 있어서, 상기 제1절연막은 200-800Å 두께로 형성하는 것을 특징으로 하는 반도체 장치의 다층 배선구조의 제조방법.The method of manufacturing a multilayer wiring structure of a semiconductor device according to claim 3, wherein said first insulating film is formed to a thickness of 200-800 Å. 제3항에 있어서, 상기 제2절연막은 양극산화방식으로 형성하는 것을 특징으로 하는 반도체 장치의 다층 배선구조의 제조방법.The method for manufacturing a multilayer wiring structure of a semiconductor device according to claim 3, wherein said second insulating film is formed by anodizing. 제3항에 있어서, 상기 제2절연막은 200-1500Å 두께로 형성하는 것을 특징으로 하는 반도체 장치의 다층 배선구조의 제조방법.The method of manufacturing a multilayer wiring structure of a semiconductor device according to claim 3, wherein said second insulating film is formed to a thickness of 200-1500 Å. 제3항에 있어서, 상기 제1금속배선은 상기 복수 개의 콘택홀 상에 형성하되, 콘택홀을 하나씩 건너뛰어 형성되도록 하는 것을 특징으로 하는 반도체 장치의 다층 배선구조의 제조방법.The method of claim 3, wherein the first metal wiring is formed on the plurality of contact holes, and the contact holes are formed by skipping the contact holes one by one. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950046087A 1995-12-01 1995-12-01 Multi-layer interconnection structure of semiconductor device and method for manufacturing thereof KR0179707B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950046087A KR0179707B1 (en) 1995-12-01 1995-12-01 Multi-layer interconnection structure of semiconductor device and method for manufacturing thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950046087A KR0179707B1 (en) 1995-12-01 1995-12-01 Multi-layer interconnection structure of semiconductor device and method for manufacturing thereof

Publications (2)

Publication Number Publication Date
KR970053507A true KR970053507A (en) 1997-07-31
KR0179707B1 KR0179707B1 (en) 1999-04-15

Family

ID=19437390

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950046087A KR0179707B1 (en) 1995-12-01 1995-12-01 Multi-layer interconnection structure of semiconductor device and method for manufacturing thereof

Country Status (1)

Country Link
KR (1) KR0179707B1 (en)

Also Published As

Publication number Publication date
KR0179707B1 (en) 1999-04-15

Similar Documents

Publication Publication Date Title
KR920005304A (en) Wiring connection structure of semiconductor integrated circuit device and its manufacturing method
KR950004532A (en) Highly Integrated Semiconductor Wiring Structure and Manufacturing Method
KR920020618A (en) Wiring connection structure of semiconductor device and manufacturing method thereof
KR970060427A (en) Manufacturing method of lead frame
KR930014785A (en) Contact manufacturing method of multilayer metal wiring structure
KR960005789A (en) Method for manufacturing contact hole of semiconductor device
KR970053507A (en) Multilayer wiring structure of semiconductor device and manufacturing method thereof
KR960039288A (en) Semiconductor device manufacturing method
KR100197122B1 (en) Method for forming metal wiring in semiconductor device
KR0135254B1 (en) Metal line of semiconductor device
KR100187684B1 (en) Metal wiring forming method of semiconductor device
KR100447982B1 (en) Method for forming metal interconnection of semiconductor device using buffer layer
KR960015729A (en) Metal wiring formation method of semiconductor device
KR950027946A (en) Method for manufacturing metallization contact of semiconductor device
KR970054004A (en) Bit line formation method of semiconductor device
KR970053298A (en) Metal wiring formation method
KR960039356A (en) Method for manufacturing charge storage electrode of semiconductor device
KR950027949A (en) Wiring method of semiconductor device
KR970052385A (en) Method for forming contact hole in semiconductor device
KR960035801A (en) Manufacturing method of semiconductor device
KR970053571A (en) Semiconductor device and manufacturing method thereof
KR960019511A (en) Manufacturing Method of Semiconductor Device
KR970053560A (en) Wiring Formation Method of Semiconductor Integrated Circuits
KR19990004661A (en) Semiconductor device and manufacturing method thereof
KR950021414A (en) Connecting process between multilayer wirings of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20091028

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee