KR970053172A - Method of forming pad part of semiconductor device - Google Patents

Method of forming pad part of semiconductor device Download PDF

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Publication number
KR970053172A
KR970053172A KR1019950052281A KR19950052281A KR970053172A KR 970053172 A KR970053172 A KR 970053172A KR 1019950052281 A KR1019950052281 A KR 1019950052281A KR 19950052281 A KR19950052281 A KR 19950052281A KR 970053172 A KR970053172 A KR 970053172A
Authority
KR
South Korea
Prior art keywords
semiconductor device
forming
protective film
pad
photolithography process
Prior art date
Application number
KR1019950052281A
Other languages
Korean (ko)
Other versions
KR0169226B1 (en
Inventor
길성진
장동희
정유철
공종탁
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950052281A priority Critical patent/KR0169226B1/en
Publication of KR970053172A publication Critical patent/KR970053172A/en
Application granted granted Critical
Publication of KR0169226B1 publication Critical patent/KR0169226B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

반도체장치의 패드부 형성방법이 개시되어 있다.A method of forming a pad portion of a semiconductor device is disclosed.

본 발명은 반도체장치의 패드부 형성방법에 있어서, 패드메탈로 이루어진 접속부 위에 보호막이 형성되어 있는 웨이퍼상에 감광성 폴리이미드막을 형성하는 단계, 상기 감광성 폴리이미드를 이용한 포토리소그라피 공정을 진행하는 단계 및 상기 포토리소그라피 공정에서 형성된 폴리이미드 패턴을 식각마스크로 하부의 보호막을 에칭하여 접속부를 노출시키는 단계를 구비하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a pad part of a semiconductor device, the method comprising: forming a photosensitive polyimide film on a wafer on which a protective film is formed on a connection part made of a pad metal, performing a photolithography process using the photosensitive polyimide, and And etching the lower protective film with an etch mask on the polyimide pattern formed in the photolithography process to expose the connection portion.

따라서, 종래에 비해 간단한 과정을 통해 패드부를 형성할 수 있으므로 작업시간을 단축시켜 공정의 효율을 높이고 공정에 사용되는 화학약품 등의 소모를 줄이는 효과를 거둘 수 있다.Therefore, since the pad portion can be formed through a simple process as compared with the related art, it is possible to shorten the working time to increase the efficiency of the process and reduce the consumption of chemicals used in the process.

Description

반도체장치의 패드부 형성방법Method of forming pad part of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도 내지 제6도는 본 발명의 일 실시예에 따른 패드부 형성방법의 각 단계를 나타내는 패드부의 단면도들이다.5 to 6 are cross-sectional views of pad portions showing respective steps of the pad portion forming method according to an embodiment of the present invention.

Claims (2)

반도체장치의 패드부 형성방벙에 있어서, 패드메탈로 이루어진 접속부 위에 보호막이 형성되어 있는 웨이퍼상에 감광성 폴리이미드막을 형성하는 단계; 별도의 포토레지스트를 사용하지 않고 상기 감광성 폴리이미드를 이용하여 포토리소그라피 공정을 진행하는 단계; 및 상기 포토리소그라피 공정에서 형성된 폴리이미드 패턴을 식각마스크로 하부의 보호막을 식각하는 단계; 를 구비하여 이루어지는 것을 특징으로 하는 반도체장치의 패드부 형성방법.A method of forming a pad portion of a semiconductor device, the method comprising: forming a photosensitive polyimide film on a wafer on which a protective film is formed on a connection portion made of pad metal; Performing a photolithography process using the photosensitive polyimide without using a separate photoresist; And etching the protective film under the polyimide pattern formed by the photolithography process using an etching mask. Method for forming a pad portion of a semiconductor device comprising a. 제1항에 있어서, 상기 보호막은 실리콘 질화막(SiN)으로 이루어지는 것을 특징으로 하는 상기 반도체장치의 패드부 형성방법.The method of claim 1, wherein the protective film is made of silicon nitride (SiN). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950052281A 1995-12-19 1995-12-19 Pad form method of semiconductor apparatus KR0169226B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950052281A KR0169226B1 (en) 1995-12-19 1995-12-19 Pad form method of semiconductor apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950052281A KR0169226B1 (en) 1995-12-19 1995-12-19 Pad form method of semiconductor apparatus

Publications (2)

Publication Number Publication Date
KR970053172A true KR970053172A (en) 1997-07-29
KR0169226B1 KR0169226B1 (en) 1999-02-01

Family

ID=19441603

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950052281A KR0169226B1 (en) 1995-12-19 1995-12-19 Pad form method of semiconductor apparatus

Country Status (1)

Country Link
KR (1) KR0169226B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100542721B1 (en) * 1999-05-11 2006-01-11 삼성전자주식회사 Method for forming pattern of photosensitive polyimide and method for forming passivation layer on semiconductor device using the same
KR100719346B1 (en) * 2005-04-19 2007-05-17 삼성전자주식회사 Resistive memory cell, method for forming the same and resistive memory array using the same

Also Published As

Publication number Publication date
KR0169226B1 (en) 1999-02-01

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