KR970052894A - Polysilicon layer manufacturing method with increased grain size - Google Patents

Polysilicon layer manufacturing method with increased grain size Download PDF

Info

Publication number
KR970052894A
KR970052894A KR1019950050465A KR19950050465A KR970052894A KR 970052894 A KR970052894 A KR 970052894A KR 1019950050465 A KR1019950050465 A KR 1019950050465A KR 19950050465 A KR19950050465 A KR 19950050465A KR 970052894 A KR970052894 A KR 970052894A
Authority
KR
South Korea
Prior art keywords
amorphous silicon
silicon layer
lpcvd
grain size
polysilicon layer
Prior art date
Application number
KR1019950050465A
Other languages
Korean (ko)
Inventor
오재근
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950050465A priority Critical patent/KR970052894A/en
Publication of KR970052894A publication Critical patent/KR970052894A/en

Links

Abstract

본 발명은 반도체 소자의 그레인 크기가 증대된 폴리실리콘층 제조 방법에 관한 것으로, 그레인 크기를 증가시키기 위해 저압화학증착법(LPCVD)으로 비정질실리콘막을 형성한 다음 Si+이온 주입하여 비정질층을 더욱 비정질화 시킨다음, 열처리하여 그레인 크기가 증대된 폴리실리콘층을 제조하는 방법이다.The present invention relates to a method for manufacturing a polysilicon layer having an increased grain size of a semiconductor device. In order to increase grain size, an amorphous silicon film is formed by low pressure chemical vapor deposition (LPCVD), followed by Si + ion implantation to further amorphous the amorphous layer. Then, heat treatment is a method for producing a polysilicon layer having an increased grain size.

Description

그레인 크기가 증대된 폴리실리콘층 제조 방법Polysilicon layer manufacturing method with increased grain size

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의해 폴리실리콘층을 제조하는 단계를 도시한 도면.Figure 2 shows the steps of producing a polysilicon layer by the present invention.

Claims (10)

박막 트랜지스터 제조방법에 있어서, 실리콘기판 상부에 산화막을 중착하고, 그 상부에 저압화학증착법(LPCVD)으로 비정질실리콘층을 형성하는 단계와, 상기 비정질실리큰층으로 Si+이온 주입하여 비정질실리콘막을 더욱 비정질화 시키는 단계와, 관상로 열처리(Furnace Annealing)를 통하여 비정질실리콘층을 그레인이 조대한 폴리실리콘층으로 형성하는 단계를 포함하는 그레인 크기가 증대된 폴리실리콘층 제조 방법.In the method of fabricating a thin film transistor, an oxide film is deposited on an upper part of a silicon substrate, and an amorphous silicon layer is formed on the silicon substrate by low pressure chemical vapor deposition (LPCVD), and Si + ion is implanted into the amorphous silicon layer to further form an amorphous silicon film. And forming the amorphous silicon layer into a coarse polysilicon layer through a furnace annealing. 제1항에 있어서, 상기 저압화학중착법(LPCVD)으로 비정질실리콘층을 형성할때 초기 진공이 1×10E-7 내지 5×10E-7 torr인 것을 특징으로 하는 그레인 크기가 증대된 폴리실리콘층 제조 방법.The polysilicon layer with increased grain size according to claim 1, wherein the initial vacuum is 1x10E-7 to 5x10E-7 torr when the amorphous silicon layer is formed by LPCVD. Manufacturing method. 제1항에 있어서, 상기 저압화학중착법(LPCVD)으로 비정질실리콘층을 형성할때 중착압력이 0.1-0.5 torr인 것을 특징으로 하는 그레인 크기가 증대된 폴리실리콘층 제조 방법.2. The method of claim 1, wherein the deposition pressure is 0.1-0.5 torr when the amorphous silicon layer is formed by low pressure chemical deposition (LPCVD). 제2항에 있어서, 상기 저압화학중착법(LPCVD)으로 비정질실리콘층을 형성할때 소오스 개스는 Si2H6개스인 것을 특징으로 하는 그레인 크기가 증대된 폴리실리콘층 제조 방법.3. The method of claim 2, wherein the source gas is Si 2 H 6 gas when the amorphous silicon layer is formed by low pressure chemical deposition (LPCVD). 제2항에 있어서, 상기 저압화학중착법(LPCVD)으로 비정질실리콘층을 형성할때 중착온도는 410-500℃인 것을 특징으로 하는 그레인 크기가 증대된 폴리실리콘층 제조방법.The method of claim 2, wherein the deposition temperature is 410-500 ° C. when the amorphous silicon layer is formed by low pressure chemical deposition (LPCVD). 제1항에 있어서, 상기 Si+이온주입 에너지는 50KeV인 것을 특징으로 하는 그레인 크기가 증대된 폴리실리콘층 제조 방법.The method of claim 1, wherein the Si + ion implantation energy is 50 KeV. 제1항에 있어서, 상기 Si+이온주입양은 5×10E14 내지 5×10E15/㎠인 것을 특징으로 하는 그레인 크기가 증대된 폴리실리콘층 제조 방법.The method of claim 1, wherein the Si + ion implantation amount is 5 × 10E14 to 5 × 10E15 / cm 2. 제1항에 있어서, 상기 관상로 열처리는 550-600℃의 온도에서 실시하는 것을 특징으로 하는 그레인 크기가 증대된 폴리실리콘층 제조 방법.The method of claim 1, wherein the tubular heat treatment is carried out at a temperature of 550-600 ℃ the grain size increased polysilicon layer manufacturing method. 제1항에 있어서, 상기 관상로 열처리시 분위기는 N2개스 분위기인 것을 특징으로 하는 그레인 크기가 증대된 폴리실리콘층 제조 방법.The method of claim 1, wherein the atmosphere during heat treatment of the tubular furnace is an N 2 gas atmosphere. 제1항에 있어서, 상기 관상로 열처리기 초기 진공은 1×10E-3 내지 5×10E-3 torr인 것을 특징으로 하는 그레인 크기가 증대된 폴리실리콘층 제조 방법.The method of claim 1, wherein the tubular heat treatment machine initial vacuum is 1 × 10E-3 to 5 × 10E-3 torr. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950050465A 1995-12-15 1995-12-15 Polysilicon layer manufacturing method with increased grain size KR970052894A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950050465A KR970052894A (en) 1995-12-15 1995-12-15 Polysilicon layer manufacturing method with increased grain size

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950050465A KR970052894A (en) 1995-12-15 1995-12-15 Polysilicon layer manufacturing method with increased grain size

Publications (1)

Publication Number Publication Date
KR970052894A true KR970052894A (en) 1997-07-29

Family

ID=66594980

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950050465A KR970052894A (en) 1995-12-15 1995-12-15 Polysilicon layer manufacturing method with increased grain size

Country Status (1)

Country Link
KR (1) KR970052894A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040001846A (en) * 2002-06-29 2004-01-07 주식회사 하이닉스반도체 Method for fabricating semiconductor device with dual gate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040001846A (en) * 2002-06-29 2004-01-07 주식회사 하이닉스반도체 Method for fabricating semiconductor device with dual gate

Similar Documents

Publication Publication Date Title
US5652166A (en) Process for fabricating dual-gate CMOS having in-situ nitrogen-doped polysilicon by rapid thermal chemical vapor deposition
JPS60245173A (en) Insulated gate type semiconductor device
KR960005801A (en) Semiconductor device manufacturing method
KR920003414A (en) High melting point metal growth method
NL194524C (en) Method for manufacturing a thin film transistor.
KR960043036A (en) Process for forming a refractory metal silicide film having a uniform thickness
KR970052894A (en) Polysilicon layer manufacturing method with increased grain size
EP0641018A1 (en) Manufacturing method of semiconductor device and thin film transistor with a recrystallized thin semiconductor film
JP2920546B2 (en) Method for manufacturing same-polarity gate MIS transistor
KR960019767A (en) A field effect transistor having a gate structure formed of a nitrogen-containing silicon layer and a high melting point metal layer, and a manufacturing process thereof
JPH05275448A (en) Manufacture of thin film semiconductor device
JP2565192B2 (en) Method for manufacturing semiconductor device
KR940007975A (en) Method of manufacturing channel poly of thin film transistor
KR950021113A (en) Gate electrode formation method of semiconductor device
KR950030336A (en) Method of forming dielectric film of capacitor
KR100223275B1 (en) Method of forming polysilicon layer in semiconductor device
JP2622373B2 (en) Thin film transistor and method of manufacturing the same
KR970023879A (en) Method of manufacturing thin film transistor
JPH04186735A (en) Manufacture of semiconductor device
JPH03200319A (en) Formation of poly-crystalline silicon
KR960019594A (en) Gate electrode manufacturing method
KR960023266A (en) Polysilicon layer formation method of semiconductor device
KR970077222A (en) Manufacturing method of semiconductor device
KR960002571A (en) Gate electrode formation method of semiconductor device
KR890016662A (en) Manufacturing Method of Amorphous Silicon EEPROM Cell

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination