KR970052328A - Lead layer formation method of semiconductor device - Google Patents

Lead layer formation method of semiconductor device Download PDF

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Publication number
KR970052328A
KR970052328A KR1019950054378A KR19950054378A KR970052328A KR 970052328 A KR970052328 A KR 970052328A KR 1019950054378 A KR1019950054378 A KR 1019950054378A KR 19950054378 A KR19950054378 A KR 19950054378A KR 970052328 A KR970052328 A KR 970052328A
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KR
South Korea
Prior art keywords
conductive layer
layer
contact hole
semiconductor device
oxide film
Prior art date
Application number
KR1019950054378A
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Korean (ko)
Other versions
KR100372655B1 (en
Inventor
문환성
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950054378A priority Critical patent/KR100372655B1/en
Publication of KR970052328A publication Critical patent/KR970052328A/en
Application granted granted Critical
Publication of KR100372655B1 publication Critical patent/KR100372655B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

고집적 반도체 소자 제조 방법.Highly integrated semiconductor device manufacturing method.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

반도체 소자 제조 공정중 도선과 도선을 연결하는 경우, 종래에는 하부 도선층과 층간 절연막 및 소정의 콘택홀을 형성한 다음, 콘택홀내에 형성된 자연 산화막을 제거하기 위한 세정 공정을 거친 후, 다결정 실리콘을 증착하여 상부 도선층을 형성하게 되는데, 이때 세정 공정을 실시한 다음 도선층 증착을 위한 고정 챔버에 완전히 적재될 때까지 상당한 시간 동안 대기중에 노출되게 되므로 여전히 자연 산화막이 잔존하게 되고, 이와같이 자연 산화막이 잔존하는 상태에서 다결정 실리콘이나 알루미늄 등으로 상부 도전층을 증착하게 되면, 자연 산화막의 뭉침 현상이 일어나게 되어 접촉 면적이 줄어들게 되고, 따라서 접촉 저항이 증가하는 등의 문제점이 있었음.In the case of connecting the lead and the lead during the semiconductor device manufacturing process, conventionally, a lower lead layer, an interlayer insulating film, and a predetermined contact hole are formed, followed by a cleaning process for removing a natural oxide film formed in the contact hole, and then polycrystalline silicon is formed. The upper conductive layer is deposited to form an upper conductive layer, which is exposed to the atmosphere for a considerable time until the cleaning process is performed and then completely loaded into the fixed chamber for the conductive layer deposition. Thus, the natural oxide layer remains. When the upper conductive layer is deposited with polycrystalline silicon, aluminum, or the like, the agglomeration of the natural oxide film occurs and the contact area is reduced, thus increasing the contact resistance.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

도선층간의 연결을 위한 콘택홀을 형성한 다음, 상부 도선층을 증착하기 위한 공정챔버에서 증착 공정을 진행하기 전에 공정 챔버에 수소 플라즈마를 주입하여 콘택홀에 형성된 자연 산화막을 환원시켜 제거하므로써, 접촉 저항이 낮은 도선층을 형성할 수 있는 방법을 제공하고자 함.Contact holes are formed by forming a contact hole for connection between the conductor layers, and then injecting hydrogen plasma into the process chamber before the deposition process in the process chamber for depositing the upper conductor layer to reduce and remove the native oxide film formed in the contact hole. To provide a method to form a low resistance wire layer.

4. 발명의 주용한 용도4. Main use of the invention

반도체 소자의 자연 산화막 제거에 이용됨.Used to remove natural oxide film of semiconductor device.

Description

반도체 소자의 도선층 형성 방법Lead layer formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2B도는 본 발명의 도선층 형성 방법에 따른 공정도.2A to 2B are process charts according to the method for forming a conductor layer of the present invention.

Claims (2)

반도체 소자의 도선층을 형성하는 방법에 있어서, 반도체 기판상에 제1도전층이 형성된 구조 상에 층간 절연막을 증착하는 단계와, 포토마스크 및 식각 공정을 통해 콘택홀을 형성하는 단계와, 제2도선층을 증착하기 위한 공정 쳄버에 웨이퍼를 적재하는 단계와, 상기 공정 챔버에서 수소 이온 및 활성화된 수소 원자를 이용하여 자연 산화막을 제거하는 단계 및 전체 구조 상부에 제2도전층을 증착하는 단계를 포함해서 이루어진 도선층 형성 방법.A method of forming a conductive layer of a semiconductor device, comprising: depositing an interlayer insulating film on a structure on which a first conductive layer is formed on a semiconductor substrate, forming a contact hole through a photomask and an etching process, and Loading a wafer into a process chamber for depositing a lead layer, removing a native oxide film using hydrogen ions and activated hydrogen atoms in the process chamber, and depositing a second conductive layer over the entire structure Conductor layer formation method comprised including. 제1항에 있어서, 상기 콘택홀 형성 단계 이후에 자연 산화막 제거를 위한 세정 공정을 실시하는 단계를 더 포함하는 것을 특징으로 하는 도선층 형성 방법.The method of claim 1, further comprising performing a cleaning process for removing a natural oxide layer after the contact hole forming step. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950054378A 1995-12-22 1995-12-22 Method for forming metal layer of semiconductor device KR100372655B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950054378A KR100372655B1 (en) 1995-12-22 1995-12-22 Method for forming metal layer of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950054378A KR100372655B1 (en) 1995-12-22 1995-12-22 Method for forming metal layer of semiconductor device

Publications (2)

Publication Number Publication Date
KR970052328A true KR970052328A (en) 1997-07-29
KR100372655B1 KR100372655B1 (en) 2003-05-09

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100777535B1 (en) * 2007-06-01 2007-11-16 전황섭 Advertising pannel using a light source for led lamp

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190093214A1 (en) * 2017-09-22 2019-03-28 Applied Materials, Inc. Native or uncontrolled oxide reduction by a cyclic process of plasma treatment and h* radicals

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100777535B1 (en) * 2007-06-01 2007-11-16 전황섭 Advertising pannel using a light source for led lamp

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Publication number Publication date
KR100372655B1 (en) 2003-05-09

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