KR970051984A - 화합물 반도체의 에피텍시 성장방법 - Google Patents

화합물 반도체의 에피텍시 성장방법 Download PDF

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KR970051984A
KR970051984A KR1019950052670A KR19950052670A KR970051984A KR 970051984 A KR970051984 A KR 970051984A KR 1019950052670 A KR1019950052670 A KR 1019950052670A KR 19950052670 A KR19950052670 A KR 19950052670A KR 970051984 A KR970051984 A KR 970051984A
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South Korea
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compound semiconductor
growth method
type
epitaxial growth
ingaas
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KR1019950052670A
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KR0171376B1 (ko
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노정래
김성복
이일항
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양승택
한국전자통신연구원
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Priority to US08/716,646 priority patent/US5858818A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/065—Gp III-V generic compounds-processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/072—Heterojunctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/11—Metal-organic CVD, ruehrwein type
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/16—Superlattice

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

본 발명은 인듐갈륨아세나이츠의 P-N 접합구조의 형성방법에 관한것으로 특히, 사전 열분해 공정을 거치지 않은 V 족 화합물의 원료 기체와 사전열분해 공정을 거친 Ⅲ 족의 화합물을 원료기체로 하여 N 형 전도특성을 갖는 인듐갈륨아세나이드와 P 형의 전기전도도를 나타내는 InGaAs 를 성장온도의 조절만으로 형성하는 방법에 관한것이다.

Description

화합물 반도체의 에피텍시 성장방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 에피텍시 성장시 성장온도 대 캐리어 농도의 분포도를 나타낸 그래프.

Claims (5)

  1. 화합물 반도체기판상에 화합물 반도체를 에피텍시 성장하는 방법에 있어서, 반응로내에 화합물 반도체기판을 실장하고, 상기 반응로내에 사전 열분해 공정을 거치지 않은 Ⅴ 족과 사전열분해된 Ⅲ 족의 유기 금속 원료기체를 주입하고 성장온도를 조절하여 p 형 또는 n 형 화합물 반도체를 형성함을 특징으로 하는 화합물 반도체의 에피텍시 성장방법.
  2. 제1항에 있어서, p 형 화합물 반도체를 저온에서 성장하고 높은 성장온도에서 n 형의 화합물 반도체를 성장시키는 것을 특징으로 하는 화합물 반도체의 에피텍시 성장방법.
  3. 제2항에 있어서, p 형 화합물 반도체로서 InGaAs 화합물 반도체박막의 증착시 성장온도를 450℃ 이하로 유지하는 것을 특징으로 하는 화합물 반도체의 에피텍시 성장방법.
  4. 제2항에 있어서, n 형 화합물 반도체로서 InGaAs 화합물 반도체 형성시는 성장온도를 450℃ 이상의 유지하는 것을 특징으로 하는 화합물 반도체의 에피텍시 성장방법.
  5. 제1항에 있어서, 상기 Ⅲ 족 유기금속 원료로서 트리메칠인듐(trimethyindum : TMI) 과 트리에칠갈륨(triethygallium : TEG) 이 사용되고, Ⅴ 족 원료로서 모노에칠아세닌(monoethyiarseine : MEA) 가 사용됨을 특징으로 하는 화합물 반도체의 에피텍시 성장방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950052670A 1995-12-20 1995-12-20 화합물 반도체의 에피택시 성장방법 KR0171376B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019950052670A KR0171376B1 (ko) 1995-12-20 1995-12-20 화합물 반도체의 에피택시 성장방법
US08/716,646 US5858818A (en) 1995-12-20 1996-09-16 Formation of InGaSa p-n Junction by control of growth temperature

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950052670A KR0171376B1 (ko) 1995-12-20 1995-12-20 화합물 반도체의 에피택시 성장방법

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KR970051984A true KR970051984A (ko) 1997-07-29
KR0171376B1 KR0171376B1 (ko) 1999-03-30

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US7345327B2 (en) 2000-11-27 2008-03-18 Kopin Corporation Bipolar transistor
JP2004521485A (ja) 2000-11-27 2004-07-15 コピン コーポレーション 格子整合されたベース層を有するバイポーラトランジスタ
US6847060B2 (en) * 2000-11-27 2005-01-25 Kopin Corporation Bipolar transistor with graded base layer
US6800879B2 (en) 2001-01-08 2004-10-05 Kopin Corporation Method of preparing indium phosphide heterojunction bipolar transistors
US7523394B2 (en) * 2002-06-28 2009-04-21 Microsoft Corporation Word-processing document stored in a single XML file that may be manipulated by applications that understand XML
US7935616B2 (en) * 2004-06-17 2011-05-03 Burgener Ii Robert H Dynamic p-n junction growth
US7566948B2 (en) * 2004-10-20 2009-07-28 Kopin Corporation Bipolar transistor with enhanced base transport

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JPS6055478B2 (ja) * 1982-10-19 1985-12-05 松下電器産業株式会社 気相成長方法
WO1987003740A1 (en) * 1985-12-09 1987-06-18 Nippon Telegraph And Telephone Corporation Process for forming thin film of compound semiconductor
US5578521A (en) * 1986-11-20 1996-11-26 Nippondenso Co., Ltd. Semiconductor device with vaporphase grown epitaxial
JP2560562B2 (ja) * 1991-04-30 1996-12-04 住友化学工業株式会社 エピタキシャル成長化合物半導体結晶
JP3156326B2 (ja) * 1992-01-07 2001-04-16 富士通株式会社 半導体成長装置およびそれによる半導体成長方法

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US5858818A (en) 1999-01-12

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