KR970051356A - Flash memory device - Google Patents

Flash memory device Download PDF

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Publication number
KR970051356A
KR970051356A KR1019950052509A KR19950052509A KR970051356A KR 970051356 A KR970051356 A KR 970051356A KR 1019950052509 A KR1019950052509 A KR 1019950052509A KR 19950052509 A KR19950052509 A KR 19950052509A KR 970051356 A KR970051356 A KR 970051356A
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KR
South Korea
Prior art keywords
signal
voltage
enable
generating
memory device
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Application number
KR1019950052509A
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Korean (ko)
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KR100208438B1 (en
Inventor
심현수
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950052509A priority Critical patent/KR100208438B1/en
Publication of KR970051356A publication Critical patent/KR970051356A/en
Application granted granted Critical
Publication of KR100208438B1 publication Critical patent/KR100208438B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • G11C29/82—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for EEPROMs

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  • Read Only Memory (AREA)

Abstract

본 발명은 플래쉬 메모리 장치에 관한 것으로서, 리던던시 셀 블럭을 선택하기 위한 퓨즈셀을 멀티 레벨셀로 사용하므로써, 칩 면적을 줄일 수 있는 플래쉬 메모리 장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device, and more particularly, to a flash memory device capable of reducing chip area by using a fuse cell for selecting a redundant cell block as a multi-level cell.

* 선택도 : 제2도* Selectivity: 2nd degree

Description

플래쉬 메모리 장치Flash memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 플래쉬 메모리 장치의 회로도,2 is a circuit diagram of a flash memory device according to the present invention;

제3도는 본 발명에 따른 전압발생 수단의 블럭도.3 is a block diagram of a voltage generating means according to the present invention.

Claims (6)

플래쉬 메모리 장치에 있어서, 멀티레벨 셀 블럭과, 어드레스 신호에 따라 워하는 전압을 발생하여 상기 멀티 레벨 셀 블럭중 한 셀 이상을 구동시키기위한 전압발생 수단과, 상기 멀티레벨 셀블럭에 접속되어 프로그램 확인시 턴온되는 스의칭 수단과, 상기 전압발생 수단에 의해 선택된 멀티레벨 셀의 상태에 따라 리던던시 셀블럭을 구동하는 신호를 생성하기 위한 인에이블 신호 생성수단으로 구성되는 것을 특징으로 하는 플래쉬 메모리 장치.A flash memory device comprising: a multilevel cell block, voltage generation means for generating a voltage to be woken in response to an address signal to drive one or more cells of the multilevel cell block, and a program check connected to the multilevel cell block. And a enable signal generating means for generating a signal for driving a redundancy cell block in accordance with the state of the multilevel cell selected by the voltage generating means. 제1항에 있어서, 상기 인에이블 신호 생성수단은 상기 프로그램 확인신호 및 상기 전압발생 수단의 출력신호에 따라 인에이블신호를 생성하는 제1인에이블신호 생성수단과, 상기 프로그램 확인신호 및 상기 전압발생 수단의 출력신호 및 제1인에이블제어신호에 따라 제2인에이블신호를 생성하는 제2인에이블신호 생성수단과, 상기 프로그램 확인신호 및 상기 전압발생 수단의 출력신호 및 제1인에이블제어신호, 제2인에이블제어신호에 따라 제3인에이블신호를 생성하는 제3인에이블제어신호, 제N-1인에이블제어신호에따라 제N인 에이블 신호를 생성하는 제N인에이블신호 생성수단으로 구성되는 것을 특징으로 하는 플래쉬 메모리 장치.The method of claim 1, wherein the enable signal generating means comprises: first enable signal generating means for generating an enable signal in accordance with an output signal of the program confirmation signal and the voltage generation means, the program confirmation signal and the voltage generation; Second enable signal generating means for generating a second enable signal in accordance with an output signal of the means and a first enable control signal, an output signal of the program confirmation signal and the voltage generating means and a first enable control signal, A third enable control signal for generating a third enable signal in accordance with the second enable control signal, and an Nth enable signal generation means for generating an N in enable signal in accordance with the N-1 enable control signal. Flash memory device, characterized in that. 제1항에 있어서, 상기 멀티레벨 셀블럭의 멀티레벨 셀은 문턱전압이 높은 순서대로 배열되는 것을 특징으로 하는 플래쉬 메모리 장치.The flash memory device as claimed in claim 1, wherein the multilevel cells of the multilevel cell block are arranged in order of high threshold voltage. 제1항에 있어서, 상기 멀티레벨 셀블럭의 멀티레벨 셀은 프로그램 동작시 반전된 프로그램 신호를입력으로하는 상기 스읫칭 수단에 의해 전원과 분리되도록 구성되는 것을 특징으로 하는 플래쉬 메모리 장치.2. The flash memory device according to claim 1, wherein the multilevel cells of said multilevel cell block are configured to be separated from a power supply by said switching means for inputting an inverted program signal during a program operation. 제1항에 있어서, 상기 전압발생 수단은 독출시 입력되는 어드레스에 의해 임의의 전압레벨을 발생시키며 프로그램 동작시에는 프로그램시 게이트전압을 발생시키도록 구성되는 것을 특징으로 하는 플래쉬 메모리 장치.2. The flash memory device as claimed in claim 1, wherein the voltage generating means generates an arbitrary voltage level by an address input during reading and generates a gate voltage during programming during a program operation. 제1항에 있어서, 상기 전압발생 수단의 출력신호는 상기 멀티레벨 셀의 콘트롤 게이트에일괄접속되도록 구성되는 것을 특징으로 하는 플래쉬 메모리 장치.2. The flash memory device according to claim 1, wherein an output signal of the voltage generating means is configured to be connected to a control gate of the multilevel cell. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950052509A 1995-12-20 1995-12-20 Flash memory device KR100208438B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950052509A KR100208438B1 (en) 1995-12-20 1995-12-20 Flash memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950052509A KR100208438B1 (en) 1995-12-20 1995-12-20 Flash memory device

Publications (2)

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KR970051356A true KR970051356A (en) 1997-07-29
KR100208438B1 KR100208438B1 (en) 1999-07-15

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KR1019950052509A KR100208438B1 (en) 1995-12-20 1995-12-20 Flash memory device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9111616B2 (en) 2006-09-13 2015-08-18 Samsung Electronics Co., Ltd. Multi-bit flash memory device and memory cell array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9111616B2 (en) 2006-09-13 2015-08-18 Samsung Electronics Co., Ltd. Multi-bit flash memory device and memory cell array

Also Published As

Publication number Publication date
KR100208438B1 (en) 1999-07-15

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