KR970051244A

KR970051244A - Power line arrangement method of semiconductor memory device

Info

Publication number: KR970051244A
Application number: KR1019950057152A
Authority: KR
Inventors: 최종현
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-12-26
Filing date: 1995-12-26
Publication date: 1997-07-29

Abstract

반도체 메모리장치의 전원선 배치방법, 특히 서브워드라인 구조를 갖는 반도체 메모리장치의 전원선 배치방법이 포함되어 있다. 본 발명은 복수개의 메모리 셀 어레이 블락과 , 메인워드라인과, 서브워드라인과, 상기 서브워드라인을 드라이브하는 영역을 갖는 반도체 메모리장치에 있어서, 상기 서브워드라인 드라이버 영역에 전원을 공급하기 위해 메모리 어레이 셀위로 상기 메인우드라인과 평행한 배치구조를 갖는 것을 특징으로 한다.A power line arrangement method of a semiconductor memory device, in particular, a power line arrangement method of a semiconductor memory device having a subword line structure is included. The present invention provides a semiconductor memory device having a plurality of memory cell array blocks, a main word line, a sub word line, and an area for driving the sub word line, the memory for supplying power to the sub word line driver area. And an arrangement structure parallel to the main wood lines on the array cells.

따라서 본 발명은 메인워드라인과 메인워드라인 사이를 통해 메모리 어레이 셀을 적절한 용도로 사용하기 위한 필요전원을 공급함으로써, 칩 크기를 줄일 수 있고 메모리 어레이에 전원 공급능력을 극대화 할 수 있다.Therefore, the present invention can reduce the chip size and maximize the power supply capability to the memory array by supplying the necessary power for proper use of the memory array cell between the main word line and the main word line.

Description

Power line arrangement method of semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 서브워드라인 구조상의 전원선 배치방법,2 is a method for arranging power lines on a subword line structure according to the present invention;

제3도는 본 발명의 실시예에 의한 서브워드라인 드라이버 회로.3 is a subword line driver circuit according to an embodiment of the present invention.

Claims

A semiconductor memory device having a plurality of memory cell array blocks, a main word line, a sub word line, and an area for driving the subword line, the semiconductor memory device comprising: a memory cell array block configured to supply power to the subword line driver area And a disposition structure parallel to the main word line.

2. The power supply line of claim 1, wherein a power supply line having a configuration parallel to the main word line over the memory array cell is a power source used to amplify the data to access data of the memory array cell. A power line arrangement method of a semiconductor memory device.

※ Note: The disclosure is based on the initial application.