KR970023389A - Semiconductor memory cell placement method - Google Patents

Semiconductor memory cell placement method Download PDF

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Publication number
KR970023389A
KR970023389A KR1019950034946A KR19950034946A KR970023389A KR 970023389 A KR970023389 A KR 970023389A KR 1019950034946 A KR1019950034946 A KR 1019950034946A KR 19950034946 A KR19950034946 A KR 19950034946A KR 970023389 A KR970023389 A KR 970023389A
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KR
South Korea
Prior art keywords
semiconductor memory
memory cell
placement method
cell placement
cell array
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Application number
KR1019950034946A
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Korean (ko)
Inventor
김두응
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950034946A priority Critical patent/KR970023389A/en
Publication of KR970023389A publication Critical patent/KR970023389A/en

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Abstract

반도체 메모리 장치에 관한 것으로, 특히 리던던시 중심부(Row Redundancy Cell Array)를 주변회로부와 중심부(Cell Array) 사이에 배치하지 않고 노말 중심부와 노말 중심부 사이에 배치하여 리페처(Repair) 효율을 증가시킬 수 있다.In particular, the present invention relates to a semiconductor memory device. In particular, a redundancy cell array may be disposed between a normal center and a normal center instead of a peripheral circuit and a cell array to increase repair efficiency. .

Description

반도체 메모리 셀 배치 방법Semiconductor memory cell placement method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 의한 반도체 메모리 셀 배치 방법에 있어서 로 리던던시 중심부(Row Redundancy Cell Array)의 레이아웃(Layout) 배치도를 나타낸다,3 is a layout diagram of a layout of a low redundancy cell array in the semiconductor memory cell arrangement method according to the present invention.

제4도는 본 발명의 다른 실시예에 의한 반도체 메모리 셀 배치 방법에 있어서 로 리던던시 중심부(Row Redundancy Cell Array)의 레이아웃(Layout) 배치도를 나타낸다.FIG. 4 is a layout diagram of a low redundancy cell array in the semiconductor memory cell arrangement method according to another embodiment of the present invention.

Claims (1)

주변 회로부와 노말 중심부(Normal Cell Array), 로 리던던시 중심부(Row Redundancy Cell Array)로 구성된 반도체 메모리 장치에 있어서, 상기 로 리던던시 중심부가 상기 노말 중심부와 노말 중심부 사이에 레이아웃(Layout) 배치됨을 그 특징으로 하는 반도체 메모리 셀 배치 방법.A semiconductor memory device comprising a peripheral circuit portion, a normal cell array, and a low redundancy cell array, wherein the low redundancy center is laid out between the normal center and the normal center. A semiconductor memory cell placement method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950034946A 1995-10-11 1995-10-11 Semiconductor memory cell placement method KR970023389A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950034946A KR970023389A (en) 1995-10-11 1995-10-11 Semiconductor memory cell placement method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950034946A KR970023389A (en) 1995-10-11 1995-10-11 Semiconductor memory cell placement method

Publications (1)

Publication Number Publication Date
KR970023389A true KR970023389A (en) 1997-05-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950034946A KR970023389A (en) 1995-10-11 1995-10-11 Semiconductor memory cell placement method

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990001473A (en) * 1997-06-16 1999-01-15 윤종용 Semiconductor memory device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990001473A (en) * 1997-06-16 1999-01-15 윤종용 Semiconductor memory device and manufacturing method thereof

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