KR970051231A

KR970051231A - Pseudo Latched Sense Amplifiers in Semiconductor Devices

Info

Publication number: KR970051231A
Application number: KR1019950055036A
Authority: KR
Inventors: 배용철
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-12-22
Filing date: 1995-12-22
Publication date: 1997-07-29
Also published as: KR0163541B1

Abstract

여기서는 입력 신호들의 레벨들이 바뀌면 프리챠지 동작없이도 래치상태로부터 벗어나게 되어 출력 신호들 각각이 입력 신호들 각각의 레벨에 대응되는 레벨을 갖게 되면서도 입력 신호들이 변하지 않는 래치 상태일 때 전류 소모가 없는 의사 래치형 감지 증폭기(peudo latch type sense amplifier)가 개시된다. 이 의사 래치형 감지 증폭기는 작은 스윙 폭을 갖는 두 입력 전압 신호들(IN1, IN2)이 인가되는 입력부(MN1, MN2)와, 입력 전압 신호들(IN1, IN2)을 증폭하여 래치하는 래치부(MP1, MP2, MN3, MN4)와, 이 회로의 구동을 위한 인에이블 신호(PLE)가 소정의 전압 레벨을 갖는 것에 응답하여 이 회로에 전류를 공급하는 전류원(MN5)과, 디스에이블 상태에서 출력 노드들(N1, N2)을 프리챠징하는 프리챠지부(MP3, MP4) 및, 제1 및 제2출력 노드들(N1, N2)과 전원 전압(Vcc) 노드 사이에 연결되고 입력 전압 신호들(IN1, IN2)의 레벨에 따라 전원 전압(Vcc)이 제1 및 제2출력 노드(N1, N2)로 인가되도록 하거나 인가되지 않도록 하는 스위칭부(MP5, MP6)로 구성된다.Here, when the levels of the input signals are changed, they are released from the latch state without the precharge operation, so that each output signal has a level corresponding to the level of each of the input signals, but there is no current consumption when the input signals are not changed in the latch state. A sense latch type sense amplifier is disclosed. The pseudo latching sense amplifier includes an input unit MN1 and MN2 to which two input voltage signals IN1 and IN2 having a small swing width are applied, and a latch unit amplifying and latching the input voltage signals IN1 and IN2 ( MP1, MP2, MN3, MN4, current source MN5 for supplying current to the circuit in response to the enable signal PLE for driving the circuit having a predetermined voltage level, and output in the disabled state. Precharge units MP3 and MP4 precharging the nodes N1 and N2 and between the first and second output nodes N1 and N2 and the power supply voltage Vcc node and input voltage signals According to the levels of IN1 and IN2, the power supply voltage Vcc is configured to be switched to the first and second output nodes N1 and N2 or to the switching units MP5 and MP6.

Description

Pseudo Latched Sense Amplifiers in Semiconductor Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 의사 래치형 감지 증폭기의 일 실시예를 나타낸 회로도.3 is a circuit diagram illustrating an embodiment of a pseudo latching sense amplifier according to the present invention.

제4도는 본 발명에 따른 의사 래치형 감지 증폭기의 다른 실시예를 나타낸 회로도.4 is a circuit diagram showing another embodiment of a pseudo latching sense amplifier according to the present invention.

Claims

A first power supply voltage node connected between a first power supply voltage node to which the first power supply voltage is applied and a second power supply voltage node to which the second power supply voltage is applied, and configured to receive first and second input voltage signals having different levels, respectively; Latched type having first and second output nodes for outputting first and second input nodes and two voltage signals amplified corresponding to the first and second input voltage signals as first and second output signals, respectively Sense amplification means; The first input voltage connected between the first and second output nodes and the first power supply voltage, in response to the first input voltage signal having a first level and the second input voltage signal having a second level; And causing the second output nodes to be electrically insulated from the first power supply voltage node, wherein the first input voltage signal has the second level and the second input voltage signal has the first level. And a switching means for causing the first and second output nodes to be electrically connected with the first power supply voltage node.

2. The pseudo latching sense amplifier of claim 1, wherein the first power supply voltage is Vcc and the second power supply voltage is Vss.

3. The switching circuit of claim 2, wherein the switching means comprises: a first PMOS transistor having a gate connected to the first input node, a source connected to the first power supply voltage node, and a drain connected to the first output node; And a second PMOS transistor having a gate connected to an input node, a source connected to the first power supply voltage node, and a drain connected to the second output node.

4. The method of claim 3, wherein one of the first and second levels is at least a level of at least Vcc-V _TP (where V _TP is a threshold voltage of the PMOS) and the other is at least a level of at least Vcc-V _TP. Pseudo Latched Sense Amplifier in Semiconductor Devices.

The pseudo latch-type sense amplifier of claim 1, wherein the first power supply voltage is Vss and the second power supply voltage is Vcc.

6. The switching circuit of claim 5, wherein the switching means comprises: a first NMOS transistor having a gate connected to the first input node, a source connected to the first power supply voltage node, and a drain connected to the first output node; And a second NMOS transistor having a gate connected to an input node, a source connected to the first power supply voltage node, and a drain connected to the second output node.

7. The semiconductor device of claim 6, wherein any one of the first and second levels is at least a level above V _TN (where V _TN is a threshold voltage of the NMOS) and the other is at least a level below V _TN . Pseudo Latched Sense Amplifier.

※ Note: The disclosure is based on the initial application.