KR970051111A - Memory control circuit - Google Patents

Memory control circuit Download PDF

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Publication number
KR970051111A
KR970051111A KR1019950052262A KR19950052262A KR970051111A KR 970051111 A KR970051111 A KR 970051111A KR 1019950052262 A KR1019950052262 A KR 1019950052262A KR 19950052262 A KR19950052262 A KR 19950052262A KR 970051111 A KR970051111 A KR 970051111A
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KR
South Korea
Prior art keywords
signal
cas
ras
address
output
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KR1019950052262A
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Korean (ko)
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KR0185786B1 (en
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서광수
최윤식
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김주용
현대전자산업 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

본 발명은 1회의 어드레스 구동으로 라인 단위의 데이타를 메모리에 기록 및 독출할 수 있도록 하는 것이다.The present invention allows writing and reading of data in units of lines into a memory by one address driving.

본 발명은 한번의 버스 사용요청으로 사용권을 획득하였을 경우에 데이타를 기록 및 독출할 어드레스를 구동하고 연속적으로 데이타를 4회 기록 및 독출하여 라인 단위로 데이타를 전송하는 것으로서 메모리를 블록 단위로 구획하고, 구획한 블록 단위의 영역중에서 하나의 영역을 RAS 및 CAS 신호로 선택하며, RAS 신호에 따라 메모리의 행방향 영역이 선택되었을 경우에 하나의 RAS 어드레스 신호를 발생하여 메모리에 인가함과 아울러 CAS 신호에 의해 메모리의 열방향 어드레스가 선택되었을 경우에 4개의 CAS 어드레스를 연속적으로 발생 및 메모리에 인가하여 소정의 데이타를 기록 및 독출하며, 연속적으로 발생하는 4개의 CAS 어드레스는 외부 입력 어드레스를 이용하여 발생시킨다.The present invention divides the memory into block units by driving an address to write and read data when the license is acquired by one bus use request, and by sequentially writing and reading the data four times to transfer data in line units. In this case, one area is selected as the RAS and CAS signal among the divided block unit areas. When the row direction area of the memory is selected according to the RAS signal, one RAS address signal is generated and applied to the memory. When the column address of the memory is selected by means of four consecutive CAS addresses are generated and applied to the memory to write and read predetermined data, and four consecutive CAS addresses are generated by using an external input address. Let's do it.

Description

메모리 제어회로Memory control circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 메모리 제어회로의 전체 구성을 보인 회로도.2 is a circuit diagram showing the overall configuration of the memory control circuit of the present invention.

Claims (6)

미리 구획된 다수의 영역중에서 RAS 및 CAS 신호에 따라 하나의 영역이 선택되어 어드레스 신호에 따라 데이타를 기록 및 독출하는 메모리(10)와, 데이타 스트로브 신호(/DS)를 지연시켜 RAS 신호를 생성하는 RAS 신호 생성부(20)와, 상기 RAS 신호 생성부(20)의 출력신호를 지연시켜 CAS 신호를 생성하는 CAS 신호 생성부(30)와, 어드레스(A27,A28)에 따라 각기 4비트의 RAS 및 CAS 신호 발생을 제어하는 멀티플렉서(40)와, 상기 상기 RAS 신호 생성부(20), CAS 신호 생성부(30)의 출력신호와 상기 멀티플렉서(40)의 출력신호에 따라 각기 4비트의 RAS 신호 및 CAS 신호를 발생하여 상기 메모리(10)에 인가하는 RAS/CAS 신호 발생부(50)와, 버스트 신호(/BURST), 어드레스 스트로브 신호(/AS) 및 어드레스 신호(A3,A4)에 따라 CAS 어드레스를 가변시키는 CAS 어드레스 가변부(60)와, 어드레스 신호(A26~A15)를 RAS 어드레스로 출력함과 아울러 어드레스 신호(A14~A5) 및 상기 CAS 어드레스 가변부(60)의 출력신호를 CAS 어드레스 신호로 출력하여 상기 메모리(10)에 인가하는 RAS/CAS 어드레스 발생부(70)로 구성됨을 특징으로 하는 메모리 제어회로.One area is selected from a plurality of pre-partitioned areas according to the RAS and CAS signals to generate a RAS signal by delaying the memory 10 for recording and reading data according to the address signal and the data strobe signal (/ DS). The RAS signal generator 20, the CAS signal generator 30 for delaying the output signal of the RAS signal generator 20 to generate a CAS signal, and 4 according to the addresses A 27 and A 28 . A multiplexer 40 which controls generation of bits RAS and CAS signals, and 4 bits according to output signals of the RAS signal generator 20 and CAS signal generator 30 and output signals of the multiplexer 40, respectively. A RAS / CAS signal generator 50 for generating a RAS signal and a CAS signal and applying the same to the memory 10, a burst signal (/ BURST), an address strobe signal (/ AS), and an address signal (A 3 , A). 4 ) a CAS address variable part 60 for varying the CAS address according to Outputs the calls A 26 to A 15 to the RAS address, and also outputs the address signals A 14 to A 5 and the output signals of the CAS address variable part 60 as CAS address signals to the memory 10. And a RAS / CAS address generator 70 for applying. 제1항에 있어서, RAS 신호 생성부(20)는, 클럭신호(CLK)에 따라 동작되는 플립플롭(21,22)으로 데이타 스트로브 신호(/DS)를 지연시켜 RAS 신호를 생성하는 것을 특징으로 하는 메모리 제어회로.The RAS signal generating unit 20 generates the RAS signal by delaying the data strobe signal / DS with the flip flops 21 and 22 operated according to the clock signal CLK. Memory control circuit. 제1항에 있어서, CAS 신호 생성부(30)는, RAS 신호 생성부(20)의 출력신호로 반전된 CAS 신호를 논리 곱하는 앤드 게이트(31)와, 상기 앤드 게이트(31)의 출력신호를 클럭신호(CLK)에 따라 순차적으로 지연시켜 CAS 신호로 출력하는 플립플롭(32,33)으로 구성됨을 특징으로 하는 메모리 제어회로.The CAS signal generator 30 further includes an AND gate 31 which logically multiplies the CAS signal inverted by the output signal of the RAS signal generator 20, and an output signal of the AND gate 31. And a flip-flop (32, 33) for sequentially delaying the clock signal (CLK) and outputting it as a CAS signal. 제1항에 있어서, RAS/CAS 신호 발생기(50)는, 어드레스 신호(A27,A28)를 멀티플렉싱하는 멀티플렉서(40)의 출력신호를 RAS 신호 생성부(20) 및 CAS 신호 생성부(30)의 출력신호와 각기 논리 곱하여 RAS 신호(RAS0~RAS3) 및 CAS 신호(CAS0~CAS3)를 발생하는 앤드 게이트(51~54)(55~58)로 구성됨을 특징으로 하는 메모리 제어회로.The RAS / CAS signal generator 50 of claim 1, wherein the RAS / CAS signal generator 50 outputs an output signal of the multiplexer 40 that multiplexes the address signals A 27 and A 28 to the RAS signal generator 20 and the CAS signal generator 30. And AND gates 51 to 54 and 55 to 58 that generate a RAS signal (RAS 0 to RAS 3 ) and a CAS signal (CAS 0 to CAS 3 ) by logically multiplying the output signal. Circuit. 제1항에 있어서, CAS 어드레스 가변부(60)는, 버스트 신호(/BURST) 및 어드레스 스트로브 신호(/AS)가 인버터(61)(62)를 통해 앤드 게이트(63)(64)의 일측 입력단자에 각기 인가되게 접속되고, 앤드 게이트(63)(64)의 타측 입력단자에는 상기 앤드 게이트(31)의 출력신호 및 클럭신호(CLK)가 인가되게 접속되어 앤드 게이트(63)(64)의 출력단자가 카운터(65)의 클럭단자(CK) 및 클리어 단자(CLR)에 각기 접속되며, 카운터(65)의 출력단자(Q0)(Q1)는 어드레스 신호(A3)(A4)와 함께 익스클루시브 오아 게이트(66)(67)의 입력단자에 각기 접속하는 것을 특징으로 하는 메모리 제어회로.2. The CAS address variable part 60 has a burst signal (/ BURST) and an address strobe signal (/ AS) input to one side of the AND gates 63 and 64 through the inverters 61 and 62. And the output signal of the AND gate 31 and the clock signal CLK are connected to the other input terminals of the AND gates 63 and 64 so that the AND gates 63 and 64 are connected to each other. The output terminal is connected to the clock terminal CK and the clear terminal CLR of the counter 65, respectively, and the output terminal Q 0 (Q 1 ) of the counter 65 is connected with the address signal A 3 (A 4 ). And a memory control circuit connected to the input terminals of the exclusive oar gates (66) and (67), respectively. 제1항에 있어서, RAS/CAS 어드레스 발생부(70)는, CAS 신호 생성부(30)가 CAS 신호를 발생하지 않을 경우에 동작하여 어드레스 신호(A26~A15)를 RAS 어드레스로 출력하는 플립플롭(71)과, RAS 신호 발생부(20)가 RAS 신호를 발생하지 않을 경우에 정상 동작하여 어드레스 신호(A14~A5) 및 CAS 어드레스 가변부(60)의 출력신호를 CAS 어드레스 신호로 출력하는 플립플롭(72)과, 상기 플립플롭(71,72)의 출력신호를 논리 합하여 메모리(10)에 인가하는 오아 게이트(73)로 구성됨을 특징으로 하는 메모리 제어회로.The RAS / CAS address generation unit 70 operates when the CAS signal generation unit 30 does not generate a CAS signal to output the address signals A 26 to A 15 as RAS addresses. When the flip-flop 71 and the RAS signal generator 20 do not generate a RAS signal, the flip-flop 71 and the RAS signal generator 20 operate normally to convert the address signals A 14 to A 5 and the output signals of the CAS address variable unit 60 to the CAS address signals. And a OR gate (73) for applying a logic sum of the output signals of the flip-flops (71, 72) to the memory (10). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950052262A 1995-12-19 1995-12-19 Memory control circuit KR0185786B1 (en)

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KR970051111A true KR970051111A (en) 1997-07-29
KR0185786B1 KR0185786B1 (en) 1999-04-15

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