KR970050837A - Digital V. C. Egg's Equalizer - Google Patents

Abstract

The present invention relates to an equalizer of a digital V.C.R, wherein the first delay unit 200 includes four unit delayers 201, 202, 203, and 204 for unit delaying and outputting a video signal to be reproduced and input. And the delayed video signals k (k-1), k (k-2), k (k-3), which are output from the inputted reproduction video signal k (k) and the unit delays 201, 202, 203 and 204, respectively. a multiplier 210 composed of five multipliers 211, 212, 213, 214, and 215 for multiplying k (k-4) by predetermined filter coefficients ω0, ω1, ω2, ω3, ω4 and outputting the multiplier 210, respectively. The first operation unit 220 sums the output signals, the second delay unit 270 delaying the output signal of the first operation unit, and the output signals of the first operation unit 220 are three predetermined values. A three-level discrimination unit 230 for determining and outputting one of the values, a third delay unit 240 for delaying and outputting the output signal of the three-level determination unit 230, and a third delay unit 240. The fourth delay unit 250 that delays the output signal, the output signal of the three-level determination unit 230, the output signal of the third delay unit 240 and the output signal of the fourth delay unit 250 are added up. Comparing and judging the output signal of the second operation unit 260 and the output signal of the second operation unit 260 and outputs a corrected signal accordingly if it is determined that the output signal of the second operation unit 260 is an error, otherwise The compensator 280 outputting the signal provided from the third delay unit 240 as it is, the output signal of the second delay unit 270 and the output signal of the compensator 280 are compared and detected to detect the error signal. Comparator 290, an error signal provided from the comparator 290, respective filter coefficients (ω 0, ω 1, ω 2, ω 3, ω 4) provided from the multiplier 210, and the input video signal k. (k) and the respective output signals k (k-1), k (k-2), k (k-3), k (k-4) of the delay unit 200 are calculated according to the LMS algorithm. Each filter coefficient (ω0, And a coefficient updater 300 which updates 1, ω2, ω3, and ω4) and provides them to the multiplier 210, and has an effect of preventing errors due to interference between digital signals recorded at high density. have.

Description

Digital V. C. Egg's Equalizer

As this is a public information case, the full text was not included.

3 is a block diagram showing an equalizer of a digital V. C. egg according to a preferred embodiment of the present invention.

Claims (3)

A digital V. C. equalizer for preventing distortion of a reproduction waveform due to interference between reproduction signals recorded at high density during reproduction of recorded data, wherein a predetermined number of delays for delaying and outputting a reproduced and input video signal are provided. The first delay unit 200 is composed of a group; A multiplier for multiplying the reproduced video signal to be reproduced and input and the delayed video signal output from the first delay unit 200 by predetermined filter coefficients ω 0, ω 1, ω 2, ω 3, and ω 4, respectively. 210; A first calculation unit 220 for summing and outputting respective signals provided from the multiplication unit 210; A second delay unit 270 for delaying and outputting the output signal of the first operation unit 220; A three-level discriminating unit 230 for discriminating three levels of the output signal of the first operation unit 220 and outputting a predetermined level signal according to the three levels; A third delay unit 240 for delaying and outputting the output signal of the three level determination unit 230 again; A fourth delay unit 250 delaying an output signal of the third delay unit 240; A second operation unit 260 for summing and outputting the output signal of the third level determining unit 230, the output signal of the third delay unit 240, and the output signal of the fourth delay unit 250; Comparing and determining the output signal of the second operation unit 260 and if it is determined that the output signal of the second operation unit 260 is an error, and outputs the corrected signal accordingly, otherwise provided from the third delay unit 240 A correction unit 280 for outputting the signal as it is; A comparison unit (290) for comparing and calculating the output signal of the second delay unit (270) and the output signal of the correction unit (280) to detect and output the error signal; The error signal provided from the comparator 290, the respective filter coefficients (ω 0, ω 1, ω 2, ω 3, ω 4) provided from the multiplier 210, and the respective outputs of the input video signal and the delay unit. A digital V. C. equalizer comprising a coefficient updater (300) for calculating a signal and updating the respective filter coefficients (ω0, ω1, ω2, ω3, ω4) and providing them to the multiplier (210). The method of claim 1, wherein the three-level determination unit 230 determines the output signal of the first delay unit 220 as one of three signals of 'A', 'O', '-A' Digital V. C. Egg's Equalizer. The digital V of claim 1, wherein the correction unit 280 outputs -A when the summed signal provided from the second operation unit 260 is 2A, and A when -2A. Mr. Egg's equalizer. ※ Note: The disclosure is based on the initial application.