KR970050839A - Digital V. C. Egg's Equalizer - Google Patents

Digital V. C. Egg's Equalizer Download PDF

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Publication number
KR970050839A
KR970050839A KR1019950064264A KR19950064264A KR970050839A KR 970050839 A KR970050839 A KR 970050839A KR 1019950064264 A KR1019950064264 A KR 1019950064264A KR 19950064264 A KR19950064264 A KR 19950064264A KR 970050839 A KR970050839 A KR 970050839A
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KR
South Korea
Prior art keywords
unit
signal
output
multiplier
outputting
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KR1019950064264A
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Korean (ko)
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정명환
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배순훈
대우전자 주식회사
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Priority to KR1019950064264A priority Critical patent/KR970050839A/en
Publication of KR970050839A publication Critical patent/KR970050839A/en

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  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Picture Signal Circuits (AREA)

Abstract

본 발명은 디지탈 브이.씨.알의 등화기에 관한 것으로, 재생되어 입력되는 비디오 신호를 각각 단위 지연(unit delay)시켜 출력하는 4개의 단위 지연기(201,202,203,204)로 구성되는 제1지연부(200)와, 입력되는 재생 비디오 신호(k(k)) 및 각각의 단위 지연기(201,202,203,204)로부터 출력하는 지연된 비디오 신호(k(k-1),k(k-2),k(k-3),k(k-4))를 소정의 필터 계수(ω1,ω2,ω3,ω4,ω5)와 각각 곱하여 출력하는 5개의 승산기(211,212,213,214,215)로 구성되는 승산부(210)와, 승산부(210)의 출력신호를 합산하는 연산부(220)와, 연산부(220)의 출력 신호를 3레벨의 사전 결정된 소정 값들 중 하나의 값으로 판별하여 출력하는 1레벨 판별부(230)와, 연산부(220)의 출력신호와 제1레벨 판별부(230)의 출력 신호를 비교 연산하여 그 에러 신호를 검출하여 출력하는 비교부(240)와, 비교부(240)로부터 제공되는 에러신호를 사전 결정된 3레벨의 값들 중 하나의 값으로 판별하여 출력하는 제2레벨 판별부(250)와, 제2레벨 판별부(250)의 출력신호, 승산부(210)로부터 제공되는 각각의 필터 계수(ω1,ω2,ω3,ω4,ω5), 입력되는 비디오신호k(k) 및 지연부(200)의 각각의 출력신호(k(k-1),k(k-2),k(k-3),k(k-4))를 연산하여 각각의 필터 계수(ω1,ω2,ω3,ω4,ω5)를 갱신하여 승산부(210)로 제공하는 계수 갱신부(80)를 포함하고 구성되어, 보다 간단한 연산으로 필터계수를 갱신할 수 있는 효과가 있다.The present invention relates to an equalizer of a digital V.C.R, wherein the first delay unit 200 includes four unit delayers 201, 202, 203, and 204 for unit delaying and outputting a video signal to be reproduced and input. And the delayed video signals k (k-1), k (k-2), k (k-3), which are output from the inputted reproduction video signal k (k) and the unit delays 201, 202, 203 and 204, respectively. multiplier 210 composed of five multipliers 211, 212, 213, 214, and 215 for multiplying k (k-4) by predetermined filter coefficients ω1, ω2, ω3, ω4, ω5 and outputting the multiplier 210; An operation unit 220 for summing output signals, a first level determination unit 230 for discriminating and outputting the output signal of the operation unit 220 as one of predetermined values of three levels, and an output of the operation unit 220. A comparison unit 240 that compares the signal with the output signal of the first level determination unit 230, detects and outputs the error signal, and is provided from the comparison unit 240. Each of the second level determination unit 250 and the output signal of the second level determination unit 250 and the multiplication unit 210 which determine and output the LR signal as one of three predetermined levels of values are output. Filter coefficients ω1, ω2, ω3, ω4, ω5, the input video signal k (k) and the respective output signals k (k-1), k (k-2), k ( k-3), and k (k-4)) to calculate the coefficients of the filter (ω1, ω2, ω3, ω4, ω5) and the coefficient updater 80 for providing the multiplier 210, In this case, the filter coefficient can be updated by a simpler operation.

Description

디지탈 브이.씨.알의 등화기Digital V. C. Egg's Equalizer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 바람직한 실시예에 따른 디지탈 브이.씨.알의 등화기를 나타낸 블럭도.2 is a block diagram showing an equalizer of a digital V. C. egg according to a preferred embodiment of the present invention.

Claims (1)

기록된 데이타의 재생시 고밀도로 기록된 재생 신호간의 간섭에 의한 재생 파형의 왜곡을 방지하기 위한 디지탈 브이.씨.알의 등화기에 있어서, 재생되어 입력되는 비디오 신호를 지연시켜 출력하는 소정 갯수의 지연기로 구성되는 지연부(200)와; 상기 지연부(200)로부터 출력하는 각각의 지연된 상기 비디오 신호를 소정의 필터 계수와 각각 곱하여 출력하는 승산부(210)와; 상기 승산부로부터 제공되는 각각의 신호를 합산하여 출력하는 연산부(220)와; 상기 연산부(220)의 출력 신호를 3레벨 판별하여 이에 따른 소정의 레벨 신호를 출력하는 제1레벨 판별부(230)와; 상기 연산부(220)의 출력신호와 상기 제1레벨 판별부(230)의 출력 신호를 비교 연산하여 그 에러 신호를 검출하여 출력하는 비교부(240)와; 상기 비교부(240)로부터 제공되는 에러신호를 소정의 3레벨의 신호로 판별하여 출력하는 제2레벨 판별부(250)와; 상기 제2레벨 판별부(250)의 각각의 출력신호, 상기 승산부(210)로부터 제공되는 상기 각각의 필터 계수, 상기 입력되는 비디오 신호 및 상기 지연부(200)의 각각의 출력 신호를 연산하여 상기 각각의 필터 계수를 갱신하여 상기 승산부(210)로 제공하는 계수 갱신부(260)를 포함하는 디지탈 브이.씨.알의 등화기.A digital V. C. equalizer for preventing distortion of a reproduction waveform due to interference between reproduction signals recorded at high density during reproduction of recorded data, wherein a predetermined number of delays for delaying and outputting a reproduced and input video signal are provided. A delay unit 200 formed of a group; A multiplier (210) for multiplying each delayed video signal output from the delay unit (200) by a predetermined filter coefficient; An operation unit 220 for summing and outputting respective signals provided from the multiplication unit; A first level discriminating unit 230 for determining three levels of the output signal of the calculating unit 220 and outputting a predetermined level signal according to the three levels; A comparison unit 240 for comparing and calculating the output signal of the operation unit 220 and the output signal of the first level determination unit 230 to detect and output the error signal; A second level discriminating unit 250 which discriminates and outputs an error signal provided from the comparing unit 240 as a predetermined three level signal; The respective output signal of the second level determination unit 250, the respective filter coefficients provided from the multiplier 210, the input video signal and the respective output signal of the delay unit 200 are calculated And a coefficient updater (260) for updating the respective filter coefficients and providing them to the multiplier (210). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950064264A 1995-12-29 1995-12-29 Digital V. C. Egg's Equalizer KR970050839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950064264A KR970050839A (en) 1995-12-29 1995-12-29 Digital V. C. Egg's Equalizer

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Application Number Priority Date Filing Date Title
KR1019950064264A KR970050839A (en) 1995-12-29 1995-12-29 Digital V. C. Egg's Equalizer

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KR970050839A true KR970050839A (en) 1997-07-29

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KR1019950064264A KR970050839A (en) 1995-12-29 1995-12-29 Digital V. C. Egg's Equalizer

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100282388B1 (en) * 1998-01-12 2001-02-15 구자홍 apparatus for adaptive equalizer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100282388B1 (en) * 1998-01-12 2001-02-15 구자홍 apparatus for adaptive equalizer

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