JPH0693597B2 - Automatic equalizer - Google Patents

Automatic equalizer

Info

Publication number
JPH0693597B2
JPH0693597B2 JP22755187A JP22755187A JPH0693597B2 JP H0693597 B2 JPH0693597 B2 JP H0693597B2 JP 22755187 A JP22755187 A JP 22755187A JP 22755187 A JP22755187 A JP 22755187A JP H0693597 B2 JPH0693597 B2 JP H0693597B2
Authority
JP
Japan
Prior art keywords
nth
weighting
reproduction data
autocorrelation
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP22755187A
Other languages
Japanese (ja)
Other versions
JPS6471209A (en
Inventor
勝 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22755187A priority Critical patent/JPH0693597B2/en
Publication of JPS6471209A publication Critical patent/JPS6471209A/en
Publication of JPH0693597B2 publication Critical patent/JPH0693597B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Filters That Use Time-Delay Elements (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は自動等化器に関し、特に擬似引込み防止機能を
有する自動等化器に関する。
The present invention relates to an automatic equalizer, and more particularly to an automatic equalizer having a pseudo pull-in prevention function.

〔従来の技術〕[Conventional technology]

従来,この種の自動等化器には第2図に示す様な判定帰
還形自動等化器がある。詳細はThe Bell System Techni
cal Journal Vol52,No.8,Oct,1973“Optimum Mean−Squ
are Decision Feedback Equalization"に示されてい
る。
Conventionally, as this kind of automatic equalizer, there is a decision feedback type automatic equalizer as shown in FIG. Details are The Bell System Techni
cal Journal Vol52, No.8, Oct, 1973 “Optimum Mean-Squ
are Decision Feedback Equalization ".

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上述した従来の自動等化器は判定結果をモニターしてい
ないので、擬似引き込みに陥いった時その検出が出来な
いという欠点がある。
Since the above-mentioned conventional automatic equalizer does not monitor the determination result, it has a drawback that it cannot detect the pseudo pull-in.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は上記のような欠点を解消することを目的とし、
送信データ系列と第1〜第Nの重み回路で計算された第
1〜第Nの重み係数とを受けて加算演算を行う加算器
と、該加算器の出力を受けて判定結果として再生データ
列を出力する判定器と、前記第1〜第Nの重み回路に対
応して設けられて前記再生データ列に所定の遅延を与え
る第1〜第Nの遅延回路とを含む自動等化器において、
前記前記第1〜第Nの遅延回路に対応して設けられ、対
応する遅延回路の出力と前記再生データ列とを受けて該
再生データ列の自己相関を計算する第1〜第Nの自己相
関器と、これら第1〜第Nの自己相関器で計算された自
己相関係数を受けてこれらの値をモニターし、いずれか
の自己相関係数が本来の系列にない自己相関係数である
時、これに対応する重み係数あるいはすべての重み係数
をクリアする制御回路とを備えたことを特徴とする。
The present invention aims to eliminate the above drawbacks,
An adder that performs an addition operation by receiving the transmission data sequence and the first to Nth weighting coefficients calculated by the first to Nth weighting circuits, and a reproduction data string as a determination result by receiving the output of the adder An automatic equalizer including: a determiner for outputting the first to Nth weighting circuits and first to Nth delay circuits provided corresponding to the first to Nth weighting circuits and giving a predetermined delay to the reproduction data sequence
First to Nth autocorrelations provided corresponding to the first to Nth delay circuits and receiving the output of the corresponding delay circuit and the reproduction data sequence to calculate the autocorrelation of the reproduction data sequence. And the autocorrelation coefficients calculated by the first to N-th autocorrelators are monitored to monitor these values, and any autocorrelation coefficient is an autocorrelation coefficient that is not in the original sequence At this time, a weighting coefficient corresponding to this or a control circuit for clearing all the weighting coefficients is provided.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第1図は本発明の一実施例のブロック図である。1は入
力端子,2は加算器,3−1〜3−Nはシフトレジスタ,4−
1〜4−Nは重み回路,5−1〜5−Nは乗算器,6−1〜
6−Nは積分器,7は制御回路,8は判定器,9は再生データ
出力端子をそれぞれ示す。
FIG. 1 is a block diagram of an embodiment of the present invention. 1 is an input terminal, 2 is an adder, 3-1 to 3-N are shift registers, 4−
1 to 4-N are weight circuits, 5-1 to 5-N are multipliers, 6-1 to
6-N is an integrator, 7 is a control circuit, 8 is a determiner, and 9 is a reproduction data output terminal.

次に、諸量を以下の様に定義する。Next, various quantities are defined as follows.

送信データ系列an,再生データ系列bn,等化器入力イン
パルス応答h(t),等化器入力受信信号r(t),等
化器重み係数c1,c2…cNとする。また,t=kTにおけるサ
ンプル値をサフィックスkで示す。従って, 更に,判定器入力信号のサンプル値をqkとすれば, 収束アルゴリズムとしてLMSを使用するので,タップ係
数の修正式は以下となる。
Transmission data sequence a n, reproduced data sequence b n, the equalizer input impulse response h (t), the equalizer input the received signal r (t), the equalizer weight coefficient c 1, c 2 ... c N . Also, the sample value at t = kT is indicated by the suffix k. Therefore, Furthermore, if the sample value of the decision device input signal is q k , Since LMS is used as the convergence algorithm, the modification formula of the tap coefficient is as follows.

等化器の制御が正しく行なわれており,再生データに誤
まりが無ければ, an=bn cn=hn(n=1〜N) …(4) となって(3)式はゼロとなり、重み係数は正しい値に
収束する。しかし,(3)式からわかる様に,an≠bn
つcn≠hnでも(3)式はゼロとなる場合がある。(3)
式がゼロであると重み係数の修正が行なわれず,正しく
ない値に収束しつづける(擬似引込み)。この時は
(3)式よりanとbn及びbn自身に本来無い自己相関が発
生していることがわかる。
If the equalizer is correctly controlled and there is no error in the reproduced data, then a n = b n c n = h n (n = 1 to N) (4) and (3) becomes It becomes zero and the weighting factor converges to the correct value. However, as can be seen from the expression (3), the expression (3) may be zero even if a n ≠ b n and c n ≠ h n . (3)
If the expression is zero, the weighting coefficient is not modified and the value continues to converge to an incorrect value (pseudo pull-in). At this time, it can be seen from equation (3) that an autocorrelation that is not originally present in a n , b n, and b n itself occurs.

そこで、再生データ系列bnの自己相関を計算し,その値
が本来の系列にない自己相関係数であった時,擬似引込
みが発生したと判断でき,該当する重み係数あるいは重
み係数全部をクリアすれば擬似引込みから脱出できる。
Therefore, the autocorrelation of the reproduced data sequence b n is calculated, and when the value is an autocorrelation coefficient that does not exist in the original sequence, it can be determined that pseudo pull-in has occurred, and the corresponding weight coefficient or all weight coefficients are cleared. You can escape from the pseudo pull-in.

第1図において,乗算器5−1と積分器6−1,乗算器5
−2と積分器6−2,…乗算器5−Nと積分器6−Nとの
組み合せが相関器を形成する。たとえば,積分器6−1
はE{bn・bn-1}を出力し,積分器6−NはE{bn・b
n-N}を出力する。ただしEは平均を示す。
In FIG. 1, a multiplier 5-1 and an integrator 6-1 and a multiplier 5 are provided.
-2 and integrator 6-2, ... A combination of multiplier 5-N and integrator 6-N forms a correlator. For example, integrator 6-1
Outputs E {b n・ b n-1 }, and the integrator 6-N outputs E {b n・ b
nN } is output. However, E shows an average.

制御回路7は各相関器出力をモニターし,定義された系
列に存在しない自己相関係数を検出した時,相当する重
み係数あるいは重み係数すべてをクリアーする。
The control circuit 7 monitors the output of each correlator and, when detecting an autocorrelation coefficient that does not exist in the defined series, clears the corresponding weight coefficient or all weight coefficients.

〔発明の効果〕〔The invention's effect〕

以上説明したように,本発明は通常使用される判定帰還
形等化器に自己相関と制御回路を付加することにより,
擬似引込が生じても容易に脱出できるという効果があ
る。
As described above, according to the present invention, by adding the autocorrelation and the control circuit to the normally used decision feedback equalizer,
Even if a pseudo pull-in occurs, it is possible to easily escape.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の実施例のブロック図,第2図は従来の
等化器のブロック図である。 1:入力端子,2:加算器,3−1〜3−N:シフトレジスタ,4
−1〜4−N:重み回路,5−1〜5−N:乗算器,6−1〜6
−N:積分器,9:再生データ出力端子。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional equalizer. 1: Input terminal, 2: Adder, 3-1 to 3-N: Shift register, 4
-1 to 4-N: Weighting circuit, 5-1 to 5-N: Multiplier, 6-1 to 6
−N: integrator, 9: playback data output pin.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】送信データ系列と第1〜第Nの重み回路で
計算された第1〜第Nの重み係数とを受けて加算演算を
行う加算器と、該加算器の出力を受けて判定結果として
再生データ列を出力する判定器と、前記第1〜第Nの重
み回路に対応して設けられて前記再生データ列に所定の
遅延を与える第1〜第Nの遅延回路とを含む自動等化器
において、前記前記第1〜第Nの遅延回路に対応して設
けられ、対応する遅延回路の出力と前記再生データ列と
を受けて該再生データ列の自己相関を計算する第1〜第
Nの自己相関器と、これら第1〜第Nの自己相関器で計
算された自己相関係数を受けてこれらの値をモニター
し、いずれかの自己相関係数が本来の系列にない自己相
関係数である時、これに対応する重み係数あるいはすべ
ての重み係数をクリアする制御回路とを備えたことを特
徴とする自動等化器。
1. An adder for performing an addition operation by receiving a transmission data sequence and first through Nth weighting coefficients calculated by the first through Nth weighting circuits, and a determination by receiving the output of the adder. As a result, an automatic device including a determiner that outputs a reproduction data string and first to Nth delay circuits that are provided corresponding to the first to Nth weighting circuits and give a predetermined delay to the reproduction data string Equalizers are provided corresponding to the first to Nth delay circuits, and receive an output of the corresponding delay circuit and the reproduction data sequence and calculate an autocorrelation of the reproduction data sequence. These values are monitored by receiving the Nth autocorrelator and the autocorrelation coefficients calculated by these first to Nth autocorrelators, and any one of the autocorrelation coefficients that is not in the original sequence If it is a correlation coefficient, clear the corresponding weighting coefficient or all weighting coefficients. Automatic equalizer, characterized in that a control circuit for.
JP22755187A 1987-09-11 1987-09-11 Automatic equalizer Expired - Lifetime JPH0693597B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22755187A JPH0693597B2 (en) 1987-09-11 1987-09-11 Automatic equalizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22755187A JPH0693597B2 (en) 1987-09-11 1987-09-11 Automatic equalizer

Publications (2)

Publication Number Publication Date
JPS6471209A JPS6471209A (en) 1989-03-16
JPH0693597B2 true JPH0693597B2 (en) 1994-11-16

Family

ID=16862672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22755187A Expired - Lifetime JPH0693597B2 (en) 1987-09-11 1987-09-11 Automatic equalizer

Country Status (1)

Country Link
JP (1) JPH0693597B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0770947B2 (en) * 1990-07-17 1995-07-31 日本電気株式会社 Adaptive receiver
JPH04178009A (en) * 1990-11-13 1992-06-25 Nec Corp Digital filter

Also Published As

Publication number Publication date
JPS6471209A (en) 1989-03-16

Similar Documents

Publication Publication Date Title
JP3357956B2 (en) Decision feedback equalizer
US7203233B2 (en) Adaptive coefficient signal generator for adaptive signal equalizers with fractionally-spaced feedback
TWI310637B (en) Digital signal processor, receiver, corrector and methods for the same
JPH0575498A (en) Discrimination feedback type automatic equalizer
JPH1065580A (en) Automatic equalizer
US6940898B2 (en) Adaptive coefficient signal generator for adaptive signal equalizers with fractionally-spaced feedback
US6782043B1 (en) Method and apparatus for estimating the length of a transmission line
JPH0693597B2 (en) Automatic equalizer
JP2611557B2 (en) Decision feedback type automatic equalizer
JP3391373B2 (en) Adaptive equalizer
JP3070569B2 (en) Automatic equalizer, sampling clock generation method used therefor, and recording medium
KR100262961B1 (en) Equalization Apparatus and Method Using Decision Feedback Recursive Neural Network
KR100206810B1 (en) Equalizer and ghost position discriminating method
JPS5917737A (en) Automatic waveform equalizer
JP3365593B2 (en) Timing recovery circuit
KR100207377B1 (en) Channel equalizer for a digital video cassette recorder
KR970050839A (en) Digital V. C. Egg's Equalizer
JPS596632A (en) Time division processing type controlling circuit of tap factor
JPH0795715B2 (en) Equalizer
JP2000031791A (en) Adaptive step size control adaptive filter and adaptive step size control method
KR970050838A (en) Digital V. C. Egg's Equalizer
JPH0693598B2 (en) Decision feedback equalizer
KR970050837A (en) Digital V. C. Egg's Equalizer
JPS6129163B2 (en)
JPH036688B2 (en)