JPH0770947B2 - Adaptive receiver - Google Patents

Adaptive receiver

Info

Publication number
JPH0770947B2
JPH0770947B2 JP2188318A JP18831890A JPH0770947B2 JP H0770947 B2 JPH0770947 B2 JP H0770947B2 JP 2188318 A JP2188318 A JP 2188318A JP 18831890 A JP18831890 A JP 18831890A JP H0770947 B2 JPH0770947 B2 JP H0770947B2
Authority
JP
Japan
Prior art keywords
signal
output
tap
filter
matched filter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2188318A
Other languages
Japanese (ja)
Other versions
JPH0477106A (en
Inventor
一郎 辻本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2188318A priority Critical patent/JPH0770947B2/en
Publication of JPH0477106A publication Critical patent/JPH0477106A/en
Publication of JPH0770947B2 publication Critical patent/JPH0770947B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は適応受信機に関し、特に、強度なマルチパスフ
ェージング伝搬で生じた波形歪を除去する適応受信機に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive receiver, and more particularly to an adaptive receiver that removes waveform distortion caused by strong multipath fading propagation.

(従来の技術) マルチパスフェージング回線で生じる波形歪を除去する
従来の適応受信機を第4図に示す。第4図において、40
1はタップ付き遅延素子を構成するシフトレジスタ、402
は乗算器、403は加算器、404は判定帰還形等化器(DF
E)、405は相関器である。DFE404以外の構成要素により
整合フィルタ(MF)を構成している。相関器405は、DFE
404の出力信号の判定信号とシフトレジスタ401の各
タップ上の受信信号との相関を取ることにより、整合フ
ィルタのタップ係数を求める。これらのタップ係数は伝
送系のインパルス応答の時間反転で複素共役となってい
る。すなわちシフトレジスタ401上の受信信号は、乗算
器402と加算器403において相関器405で求めたタップ係
数と畳み込まれることにより整合フィルタリングが行わ
れる。この整合フィルタの出力はDFE404に通され、符号
間干渉の除去が行われる。
(Prior Art) FIG. 4 shows a conventional adaptive receiver that removes waveform distortion caused in a multipath fading line. In FIG. 4, 40
1 is a shift register that constitutes a tapped delay element, 402
Is a multiplier, 403 is an adder, 404 is a decision feedback equalizer (DF
E) and 405 are correlators. A matched filter (MF) is composed of components other than DFE404. Correlator 405 is DFE
The tap coefficient of the matched filter is obtained by correlating the determination signal n of the output signal of 404 and the received signal on each tap of the shift register 401. These tap coefficients are complex conjugates due to the time reversal of the impulse response of the transmission system. That is, the received signal on the shift register 401 is subjected to matched filtering by being convolved with the tap coefficient obtained by the correlator 405 in the multiplier 402 and the adder 403. The output of this matched filter is passed through the DFE 404, and intersymbol interference is removed.

このMF/DFE受信機は、電子通信学会、通信方式研究会19
79年2月(CS78−203)に“マルチパス伝送路における
適応受信方式”として提案されており、厳しいマルチパ
スフェージング回線となる見通し外通信にすでに実用化
されている。この適応受信方式は、インパルス応答の前
縁(Precursor)が主応答に比べて大きくなるような非
最小位相推移フェージングに対するDFEの特性を改善す
る。整合フィルタリングにより非対称なインパルス応答
は対称化されるから、Precursorの一部の電力はインパ
ルス応答の後縁(Postcursor)に変換される。従って、
DFEの線形等化部に対する負担は減少し、DFEの等化特性
が改善される。一方、Postcursorが支配的となる最小位
相推移フェージングでは、整合フィルタリングによりPo
stcursorの一部をPrecursorに変換するから、DFEは非線
形等化に加えて線形等化も行うことになる。すなわちMF
を用いないDFE単体では判定帰還による等化だけが行わ
れるのに対し、MF/DFEではDFEが非線形等化に加えて線
形等化を行うからDFE単体の等化特性より劣化すること
になる。この適応受信方式を地上多値QAMマイクロ波伝
送に適用する場合、多値レベルの増加に伴い、この整合
フィルタリングにより歪は無視できなくなる。
This MF / DFE receiver is based on the Institute of Electronics and Communication Engineers, Communication Method Research Group 19
It was proposed in February 1979 (CS78-203) as an "adaptive reception method in a multipath transmission line", and has already been put to practical use in non-line-of-sight communication which becomes a severe multipath fading line. This adaptive reception scheme improves the DFE characteristics for non-minimum phase transition fading in which the leading edge of the impulse response is larger than the main response. Since the asymmetrical impulse response is symmetrized by the matched filtering, a part of the power of the Precursor is converted to the trailing edge (Postcursor) of the impulse response. Therefore,
The load on the DFE linear equalization unit is reduced, and the DFE equalization characteristics are improved. On the other hand, in the minimum phase shift fading in which Postcursor dominates, the Po
Since a part of stcursor is converted to Precursor, DFE will perform linear equalization in addition to nonlinear equalization. Ie MF
In the case of a DFE without using, only equalization by decision feedback is performed, whereas in MF / DFE, the DFE performs linear equalization in addition to nonlinear equalization, so it is degraded from the equalization characteristics of the DFE alone. When this adaptive reception method is applied to terrestrial multilevel QAM microwave transmission, distortion cannot be ignored due to this matched filtering as the multilevel level increases.

(発明が解決しようとする課題) 上述した従来のMF/DFE受信機では、非最小位相推移フェ
ージングに対してはDFEの等化特性を改善しているが、
最小位相推移フェージングに対してはDFE単体のものよ
り等化特性が劣化するという問題がある。
(Problems to be Solved by the Invention) In the conventional MF / DFE receiver described above, the equalization characteristic of DFE is improved with respect to non-minimum phase shift fading,
There is a problem with the minimum phase shift fading that the equalization characteristics are worse than those of the DFE alone.

そこで本発明の目的は、この最小位相推移フェージング
に対する特性劣化を解決する適応受信機を提供すること
にある。
Therefore, an object of the present invention is to provide an adaptive receiver that solves the characteristic deterioration due to the minimum phase shift fading.

(課題を解決するための手段) 本発明に係る第1の適応受信機は、トランスバーサルフ
ィルタで構成されており受信信号を入力する整合フィル
タと、該整合フィルタの出力信号を入力する判定帰還形
等化器と、該判定帰還形等化器から出力される判定信号
と前記整合フィルタの各タップ上の受信信号との相関を
取る相関器と、該相関器から出力される相関値より伝送
系のインパルス応答を監視しこの監視により得られたイ
ンパルス応答状態に対応して前記相関値に重み係数を乗
じたものを前記整合フィルタの各タップ係数として出力
する制御回路とを備えることを特徴とする。
(Means for Solving the Problem) A first adaptive receiver according to the present invention comprises a matched filter which is composed of a transversal filter and which receives a received signal, and a decision feedback type which receives an output signal of the matched filter. An equalizer, a correlator that correlates a decision signal output from the decision feedback equalizer with a received signal on each tap of the matched filter, and a transmission system based on the correlation value output from the correlator And a control circuit for monitoring the impulse response of each of the impulse response states and multiplying the correlation value by a weighting coefficient as tap coefficients of the matched filter corresponding to the impulse response state obtained by the monitoring. .

また本発明に係る第2の適応受信機は、トランスバーサ
ルフィルタで構成されており受信信号を入力する整合フ
ィルタと、該整合フィルタの出力信号を入力する判定帰
還形等化器と、該判定帰還形等化器から出力される判定
信号を入力する前記整合フィルタと同じ構成のトランス
バーサルフィルタと、前記受信信号に遅延を与える遅延
素子と、前記トランスバーサルフィルタの出力信号と前
記遅延素子の出力信号との差を取って誤差信号を生成す
る減算器と、該減算器から出力される誤差信号と前記判
定信号とから前記誤差信号が最小となるような前記トラ
ンスバーサルフィルタのタップ係数を演算するタップ係
数演算回路と、該タップ係数演算回路が生成するタップ
係数より得られるインパルス応答状態に対応して前記タ
ップ係数に重み係数を乗じたものを前記整合フィルタの
各タップ係数として出力する制御回路とを備えることを
特徴とする。
A second adaptive receiver according to the present invention comprises a matched filter which is composed of a transversal filter and which receives a received signal, a decision feedback equalizer which receives an output signal of the matched filter, and the decision feedback. Transversal filter having the same configuration as the matched filter for inputting the decision signal output from the equalizer, a delay element for delaying the received signal, an output signal of the transversal filter and an output signal of the delay element And a tap for calculating a tap coefficient of the transversal filter that minimizes the error signal from the error signal output from the subtractor and the determination signal. A coefficient calculation circuit and a weighting factor for the tap coefficient corresponding to an impulse response state obtained from the tap coefficient generated by the tap coefficient calculation circuit. Characterized in that it comprises a control circuit for outputting a respective tap coefficients of the matched filter are multiplied by.

(実施例) 次に、本発明について図面を参照して説明する。第1図
は本発明に係る第1の適応受信機の一実施例の構成を示
すブロック図である。第2図は本発明に係る第2の適応
受信機の一実施例の構成を示すブロック図である。第3
図は従来方式と本発明との動作比較のための説明図であ
る。
(Example) Next, this invention is demonstrated with reference to drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a first adaptive receiver according to the present invention. FIG. 2 is a block diagram showing the configuration of an embodiment of the second adaptive receiver according to the present invention. Third
The figure is an explanatory diagram for comparing the operations of the conventional method and the present invention.

第1図において、101は整合フィルタ(MF)、101aは5
段のシフトレジスタ、101bは乗算器、101cは加算器、10
2は判定帰還形等化器(DFE)、103は相関器、104は制御
回路、104aは制御器、104bの乗算器である。
In FIG. 1, 101 is a matched filter (MF) and 101a is 5
Stage shift register, 101b is a multiplier, 101c is an adder, 10
2 is a decision feedback equalizer (DFE), 103 is a correlator, 104 is a control circuit, 104a is a controller, and 104b is a multiplier.

第2図において、201は整合フィルタ(MF)、201aは5
段のシフトレジスタ、201bは乗算器、201cは加算器、20
2は判定帰還形等化器(DFE)、203は遅延素子、204は制
御回路、204aは制御器、204bは乗算器、205は5段のシ
フトレジスタ、206は乗算器、207は加算器、208は減算
器、209はタップ係数演算回路である。
In FIG. 2, 201 is a matched filter (MF) and 201a is 5
Stage shift register, 201b is a multiplier, 201c is an adder, 20
2 is a decision feedback equalizer (DFE), 203 is a delay element, 204 is a control circuit, 204a is a controller, 204b is a multiplier, 205 is a 5-stage shift register, 206 is a multiplier, 207 is an adder, Reference numeral 208 is a subtractor, and 209 is a tap coefficient calculation circuit.

第1図において、シフトレジスタ101aは、通常シンボル
間隔TまたはT/2に設定され、特にT/2に設定された場合
はMF101は整合フィルタリングの他に胃イミング制御機
能も有することになる。ここで、送信シンボル列をa
n(n=−∞…+∞)、MF101に入力されるまでの伝送系
のインパルス応答の離散値をhnとすると、受信信号の離
散値rnで示される。シフトレジスタ101aがT間隔の場合、シフ
トレジスタ101aの各段(タップW-2,W-1,W0,W+1,W+2)に
(1)式で表わされる受信信号rn+2,rn+1,rn,rn-1,rn-2
がそれぞれ分布する。DFE102の判定出力がの時、シ
フトレジスタ101aの各タップ上の受信信号は下記のよう
に示される。
In FIG. 1, the shift register 101a is normally set to the symbol interval T or T / 2, and particularly when it is set to T / 2, the MF 101 has a gastric iming control function in addition to the matched filtering. Where the transmission symbol string is a
n (n = -∞ ... + ∞), where h n is the discrete value of the impulse response of the transmission system until it is input to the MF101, the discrete value r n of the received signal is Indicated by. When the shift register 101a has T intervals, the reception signal r n + 2 represented by the equation (1) is provided at each stage (tap W -2 , W -1 , W 0 , W +1 , W +2 ) of the shift register 101a. , r n + 1 , r n , r n-1 , r n-2
Are distributed respectively. When the decision output of the DFE 102 is n , the received signal on each tap of the shift register 101a is shown as follows.

W-2タップ→rn+2=…h+1an+1+h+2an +h+3an-1+… W-1タップ→rn+1=…h0an+1+h+1an +h+2an-1+… W0タップ→rn=…h-1an+1+h0an +h+1an-1+… W+1タップ→rn-1=…h-2an+1+h-1an +h0an-1+… W+2タップ→rn-2=…h-3an+1+h-2an +h-1an-1+… 従って、相関器103でDFE102の判定出力とシフトレ
ジスタ101aの各タップの内容との相関を取ることによ
り、インパルス応答離散値h1を得ることができる。これ
らのタップ係数は伝送系のインパルス応答と複素共役お
よび時間反転の関係になっている。相関器103の各出力
は制御回路104内の乗算器104bに入力し、制御器104aか
らの係数g-2,g-1,g+1,g+2をそれぞれ乗ぜられる。ただ
し、MF101のセンタータップに対応するW0については乗
算は行なわない。この係数g1がすべて1の場合、制御回
路104の出力はそれぞれMF101のタップ係数W-2,W-1,W0,W
+1,W+2として乗算器101bに供給され、MF101は受信信号
とタップ係数W-2,W-1,W0,W+1,W+2とを畳み込むことによ
り整合フィルタリングを行なう。制御器104aは相関器10
3の各出力を入力としており、この信号で伝送系のイン
パルス応答状態を監視している。第3図の(a)に示す
ような主波+進み波の非最小位相推移フェージングの場
合、制御器104aの乗算器104bのタップ係数g1をすべて1
として出力する。すなわち第1図の適応受信機は第3図
(c)に示すMF/DFEと全く同じ動作を行って、第3図
(e)のように(a)のインパルス応答を対称化する。
すなわちインパルス応答の前縁(Precursor)を等価的
に減少させ、DFE102のPrecursorに対する等化能力を改
善する。一方、主波+遅れ波の最小位相推移フェージン
グの場合、制御器104aはタップ係数g1を次第に減少さ
せ、やがて零とする。ここで、この減少させる変化速度
はDFE102の追随速度より遅い。この時、第3図(b)の
ようなインパルス応答に対して整合フィルタリングを行
なわないから、DFE102の入力でのインパルス応答状態
(f)のようになっている。すなわちマルチパス歪のほ
とんどはインパルス応答の後縁(Postcursor)によるも
ので、これらはすべてDFE102の判定帰還による等化で除
去される。MF/DFEは第3図(b)に対しても(d)のよ
うにインパルス応答を対称化するから、DFE単体の特性
より劣化するが、本発明の適応受信機では最小位相推移
フェージングに対しては整合フィルタリングを施さない
からDFE単体の場合と同様に高い等化能力が得られる。
W -2 tap → r n + 2 =… h +1 a n + 1 + h +2 a n + h +3 a n-1 +… W -1 tap → r n + 1 =… h 0 a n + 1 + h +1 a n + h +2 a n-1 +… W 0 tap → r n =… h -1 a n + 1 + h 0 a n + h +1 a n-1 +… W +1 tap → r n-1 =… H -2 a n + 1 + h -1 a n + h 0 a n-1 +… W +2 taps → r n-2 =… h -3 a n + 1 + h -2 a n + h -1 a n −1 + ... Therefore, the impulse response discrete value h 1 can be obtained by correlating the determination output n of the DFE 102 and the content of each tap of the shift register 101a with the correlator 103. These tap coefficients are related to the impulse response of the transmission system by complex conjugate and time inversion. Each output of the correlator 103 is input to the multiplier 104b in the control circuit 104, and is multiplied by the coefficients g -2 , g -1 , g +1 and g +2 from the controller 104a. However, W 0 corresponding to the center tap of MF 101 is not multiplied. When the coefficients g 1 are all 1, the output of the control circuit 104 is the tap coefficients W -2 , W -1 , W 0 , W of the MF101.
+1 and W +2 are supplied to the multiplier 101b, and the MF 101 performs matching filtering by convolving the received signal and the tap coefficients W -2 , W -1 , W 0 , W +1 and W +2 . The controller 104a is the correlator 10
Each output of 3 is input, and the impulse response state of the transmission system is monitored by this signal. In the case of the non-minimum phase transition fading of the main wave + leading wave as shown in (a) of FIG. 3, all the tap coefficients g 1 of the multiplier 104b of the controller 104a are set to 1
Output as. That is, the adaptive receiver of FIG. 1 performs exactly the same operation as the MF / DFE shown in FIG. 3 (c) to make the impulse response of (a) symmetrical as shown in FIG. 3 (e).
That is, the leading edge (Precursor) of the impulse response is reduced equivalently, and the equalization ability of the DFE 102 with respect to the Precursor is improved. On the other hand, in the case of the minimum phase transition fading of the main wave + delayed wave, the controller 104a gradually reduces the tap coefficient g 1 to zero. Here, the decreasing change speed is slower than the tracking speed of the DFE 102. At this time, since matched filtering is not performed on the impulse response as shown in FIG. 3 (b), the impulse response state (f) at the input of the DFE 102 is obtained. That is, most of the multipath distortion is due to the trailing edge of the impulse response (Postcursor), and all of these are removed by equalization by the decision feedback of the DFE 102. Since the MF / DFE also makes the impulse response symmetrical with respect to FIG. 3 (b) as shown in FIG. In contrast, since matched filtering is not performed, high equalization performance can be obtained as in the case of a DFE alone.

次に、第2図の実施例について説明する。第2図におい
て、(1)式で示される受信信号はMF201と遅延素子203
に入力する。DFE202の判定出力はシフトレジスタ20
5に入力し、乗算器206で制御回路204の出力のタップ係
数W-2,W-1,W0,W+1,W+2と乗ぜられ、加算器207で合成さ
れる。この判定信号と推定インパルス応答値W1との
畳込み値は、受信信号を再生した再生波形(replica)
となっている。遅延素子203において遅延を与えられた
受信信号と加算器207の出力とは減算器208で差を取ら
れ、受信信号に対する再生波形の誤差信号eとなる。タ
ップ係数演算回路209は誤差信号eおよび判定信号
を入力して、下記に示すLMSアルゴリズムにより、イン
パルス応答推定値W1を逐次算出する。
Next, the embodiment shown in FIG. 2 will be described. In FIG. 2, the received signal represented by the equation (1) is the MF201 and the delay element 203.
To enter. The judgment output n of the DFE202 is the shift register 20.
5, the multiplier 206 multiplies the tap coefficients W −2 , W −1 , W 0 , W +1 and W +2 of the output of the control circuit 204, and the adder 207 combines them. The convolution value of this judgment signal n and the estimated impulse response value W 1 is the reproduced waveform (replica) of the received signal.
Has become. The difference between the received signal delayed by the delay element 203 and the output of the adder 207 is subtracted by the subtractor 208, which becomes the error signal e of the reproduced waveform for the received signal. The tap coefficient calculation circuit 209 uses the error signal e and the determination signal n.
And the impulse response estimation value W 1 is sequentially calculated by the LMS algorithm shown below.

▲Wn+1 1▼=▲Wn 1▼−βenn-1 …(2) ここで、βは修正係数である。(2)式において、パラ
メータnはシンボル毎の時刻を示す。シフトレジスタ20
5およびMF201のシフトレジスタ201aが共に、シンボル長
T間隔の場合、シフトレジスタ205、乗算器206、加算器
207で成るレプリカフィルタおよびMF201の遅延時間は2T
となる。またDFE202の前方等化器(線形フィルタ)をT
間隔の3タップとした時、DFE202の遅延時間は2Tとな
る。この場合、遅延素子203の遅延量を6Tに設定すれ
ば、正しいタイミング関係が成立する。以上の操作よ
り、誤差信号eの自乗平均値が最小となるように制御さ
れ、インパルス応答の推定値W1が得られる。
▲ W n + 1 1 ▼ = ▲ W n 1 ▼ -βe n · n-1 ... (2) where, β is a correction factor. In the equation (2), the parameter n indicates the time for each symbol. Shift register 20
5 and the shift register 201a of MF201 both have a symbol length T interval, shift register 205, multiplier 206, adder
Delay time of replica filter consisting of 207 and MF201 is 2T
Becomes In addition, the forward equalizer (linear filter) of the DFE202 is set to T
When the interval is 3 taps, the delay time of DFE202 is 2T. In this case, if the delay amount of the delay element 203 is set to 6T, the correct timing relationship is established. Through the above operation, the root mean square value of the error signal e is controlled to be the minimum, and the estimated value W 1 of the impulse response is obtained.

タップ係数演算回路209の出力は制御回路204に入力し、
MF201のセンタータップに対応する係数を除いて乗算器2
04bで制御器204aからの係数g-2,g-1,g+1,g+2がそれぞれ
乗ぜられる。制御器204aはタップ係数演算回路209から
のタップ係数によりインパルス応答を監視し、第1図の
実施例と同様に、非最小位相推移フェージングに対して
は、g1として1を出力し、タップ係数演算回路209から
のW1をそのまま乗算器201aに供給し、MF201に整合フィ
ルタリングを行なわせる。MF201の構成要素201a,201b,2
01cは第1図の101a,101b,101cと同じ動作を行なう。一
方、最小位相推移フェージングに対しては、g1をDFE202
が十分追随できる速さで次第に零まで減少させる。従っ
て、最小位相推移フェージングに対しては整合フィルタ
リングが行なわれずに、DFE単体の場合と同様に高い等
化能力が得られる。
The output of the tap coefficient calculation circuit 209 is input to the control circuit 204,
Multiplier 2 excluding the coefficient corresponding to the center tap of MF201
At 04b, the coefficients g -2 , g -1 , g +1 and g +2 from the controller 204a are multiplied respectively. The controller 204a monitors the impulse response by the tap coefficient from the tap coefficient calculation circuit 209, outputs 1 as g 1 for the non-minimum phase transition fading, and outputs the tap coefficient as in the embodiment of FIG. W 1 from the arithmetic circuit 209 is supplied as it is to the multiplier 201a to cause the MF 201 to perform matched filtering. MF201 components 201a, 201b, 2
01c performs the same operation as 101a, 101b, 101c in FIG. On the other hand, for minimum phase shift fading, g 1 is set to DFE202
Gradually decreases to zero at a speed that can sufficiently follow. Therefore, matched filtering is not performed for the minimum phase shift fading, and a high equalization capability is obtained as in the case of the DFE alone.

(発明の効果) 以上に説明したように、本発明は、非最小位相推移フェ
ージングに対しては整合フィルタリングを行わせること
でDFE単体の等化特性を改善し、最小位相推移フェージ
ングに対しては整合フィルタリングを行なわせないこと
によりMF/DFEの等化特性をDFE単体の等化特性より劣化
させないという効果がある。
(Effects of the Invention) As described above, the present invention improves the equalization characteristics of the DFE alone by performing matched filtering for non-minimum phase transition fading, and for minimum phase transition fading. By not performing matched filtering, the equalization characteristic of MF / DFE is not deteriorated as compared with the equalization characteristic of DFE alone.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明に係る第1の適応受信機の一実施例の構
成を示すブロック図である。第2図は本発明に係る第2
の適応受信機の一実施例の構成を示すブロック図であ
る。第3図は本発明による適応受信機と従来の適応受信
機との動作比較説明図、第4図は従来の適応受信機の構
成を示すブロック図である。 101,201……整合フィルタ(MF)、101a,201a,205,401…
…5段のシフトレジスタ、101b,104b,201b,204b,206,40
2……乗算器、101c,201c,207,403……加算器、102,202,
404……判定帰還形等化器(DFE)、103,405……相関
器、104,204……制御回路、104a,204a……制御器、203
……遅延素子、209……タップ係数演算回路。
FIG. 1 is a block diagram showing the configuration of an embodiment of a first adaptive receiver according to the present invention. FIG. 2 shows the second of the present invention.
2 is a block diagram showing the configuration of an example of the adaptive receiver of FIG. FIG. 3 is an explanatory diagram for comparing the operation of the adaptive receiver according to the present invention and the conventional adaptive receiver, and FIG. 4 is a block diagram showing the configuration of the conventional adaptive receiver. 101,201 …… Matched filter (MF), 101a, 201a, 205,401…
... 5-stage shift register, 101b, 104b, 201b, 204b, 206, 40
2 ... Multiplier, 101c, 201c, 207,403 ... Adder, 102,202,
404 ... Decision feedback equalizer (DFE), 103,405 ... Correlator, 104,204 ... Control circuit, 104a, 204a ... Controller, 203
... delay element, 209 ... tap coefficient calculation circuit.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】トランスバーサルフィルタで構成されてお
り受信信号を入力する整合フィルタと、該整合フィルタ
の出力信号を入力する判定帰還形等化器と、該判定帰還
形等化器から出力される判定信号と前記整合フィルタの
各タップ上の受信信号との相関を取る相関器と、該相関
器から出力される相関値より伝送系のインパルス応答を
監視しこの監視により得られたインパルス応答状態に対
応して前記相関値に重み係数を乗じたものを前記整合フ
ィルタの各タップ係数として出力する制御回路とを備え
ることを特徴とする適応受信機。
1. A matched filter configured by a transversal filter for inputting a received signal, a decision feedback equalizer for inputting an output signal of the matched filter, and an output from the decision feedback equalizer. A correlator that takes the correlation between the judgment signal and the received signal on each tap of the matched filter, and the impulse response of the transmission system is monitored from the correlation value output from the correlator, and the impulse response state obtained by this monitoring is obtained. An adaptive receiver comprising: a control circuit that outputs the correlation value multiplied by a weighting coefficient as each tap coefficient of the matched filter.
【請求項2】トランスバーサルフィルタで構成されてお
り受信信号を入力する整合フィルタと、該整合フィルタ
の出力信号を入力する判定帰還形等化器と、該判定帰還
形等化器から出力される判定信号を入力する前記整合フ
ィルタと同じ構成のトランスバーサルフィルタと、前記
受信信号に遅延を与える遅延素子と、前記トランスバー
サルフィルタの出力信号と前記遅延素子の出力信号との
差を取って誤差信号を生成する減算器と、該減算器から
出力される誤差信号と前記判定信号とから前記誤差信号
が最小となるような前記トランスバーサルフィルタのタ
ップ係数を演算するタップ係数演算回路と、該タップ係
数演算回路が生成するタップ係数より得られるインパル
ス応答状態に対応して前記タップ係数に重み係数を乗じ
たものを前記整合フィルタの各タップ係数として出力す
る制御回路とを備えることを特徴とする適応受信機。
2. A matched filter configured by a transversal filter for inputting a received signal, a decision feedback equalizer for inputting an output signal of the matched filter, and an output from the decision feedback equalizer. A transversal filter having the same configuration as the matched filter that inputs a determination signal, a delay element that delays the received signal, and an error signal by taking the difference between the output signal of the transversal filter and the output signal of the delay element And a tap coefficient calculation circuit for calculating a tap coefficient of the transversal filter that minimizes the error signal from the error signal output from the subtractor and the determination signal, and the tap coefficient. The matching is obtained by multiplying the tap coefficient by a weight coefficient corresponding to the impulse response state obtained from the tap coefficient generated by the arithmetic circuit. Adaptive receiver, characterized in that it comprises a control circuit for outputting a respective tap coefficients of the filter.
JP2188318A 1990-07-17 1990-07-17 Adaptive receiver Expired - Lifetime JPH0770947B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2188318A JPH0770947B2 (en) 1990-07-17 1990-07-17 Adaptive receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2188318A JPH0770947B2 (en) 1990-07-17 1990-07-17 Adaptive receiver

Publications (2)

Publication Number Publication Date
JPH0477106A JPH0477106A (en) 1992-03-11
JPH0770947B2 true JPH0770947B2 (en) 1995-07-31

Family

ID=16221508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2188318A Expired - Lifetime JPH0770947B2 (en) 1990-07-17 1990-07-17 Adaptive receiver

Country Status (1)

Country Link
JP (1) JPH0770947B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0744473B2 (en) * 1993-02-02 1995-05-15 日本電気株式会社 Demodulation system
JPH06311058A (en) * 1993-04-23 1994-11-04 Nec Corp Adaptive receiver
US5668832A (en) * 1994-03-28 1997-09-16 Nec Corporation Automatic equalizer for removing inter-code interference with fading and method of controlling tap coefficients thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6462011A (en) * 1987-09-01 1989-03-08 Nippon Telegraph & Telephone Correlation noise suppression circuit
JPH0693597B2 (en) * 1987-09-11 1994-11-16 日本電気株式会社 Automatic equalizer

Also Published As

Publication number Publication date
JPH0477106A (en) 1992-03-11

Similar Documents

Publication Publication Date Title
US5119401A (en) Decision feedback equalizer including forward part whose signal reference point is shiftable depending on channel response
US7394849B2 (en) Decision feedback equalizer with dynamic feedback control
EP0426026B1 (en) Equalizer
US5414733A (en) Decision feedback equalizer employing fixed ratio postcursor taps for minimizing noise and intersymbol interference in signals conveyed over high speed data service loop
US6285709B1 (en) Error filtering in a hybrid equalizer system
US20070230557A1 (en) Adaptive signal equalizer with adaptive error timing and precursor/postcursor configuration control
US20020150155A1 (en) Convergence speed, lowering the excess noise and power consumption of equalizers
US7016406B1 (en) Adaptation structure and methods for analog continuous time equalizers
JPH05183456A (en) Control signal generator
EP0738062A2 (en) Interference canceller employing a decision feedback equaliser
JPH0590904A (en) Control signal generating circuit
US20050232347A1 (en) Apparatus and method for noise enhancement reduction in an adaptive equalizer
CA2061930C (en) Adaptive matched pre-filtering of a decision feedback equalized input
US5159565A (en) Method for the determination of fir filter coefficients in equalizers
US7035330B2 (en) Decision feedback equalizer with dynamic feedback control
US20020027953A1 (en) Low-complexity blind equalizer
US6349112B1 (en) Adaptive equalizer compensating signal distortion on transmission path
JPH0770947B2 (en) Adaptive receiver
JP3663562B2 (en) Interference canceller and channel estimation method
JP2503715B2 (en) Adaptive receiver
KR100202944B1 (en) Equalizer
JPH0831820B2 (en) Decision feedback equalizer
WO2000059168A1 (en) Adaptive filter equalisation techniques
JP2595282B2 (en) Decision feedback equalizer
JPH03284014A (en) Decision feedback type equalizer