KR970030743A - 반도체 패키지의 리드프레임 제작방법 및 이를 이용한 반도체 패키지의 제조공정과 구조 - Google Patents
반도체 패키지의 리드프레임 제작방법 및 이를 이용한 반도체 패키지의 제조공정과 구조 Download PDFInfo
- Publication number
- KR970030743A KR970030743A KR1019950041843A KR19950041843A KR970030743A KR 970030743 A KR970030743 A KR 970030743A KR 1019950041843 A KR1019950041843 A KR 1019950041843A KR 19950041843 A KR19950041843 A KR 19950041843A KR 970030743 A KR970030743 A KR 970030743A
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- KR
- South Korea
- Prior art keywords
- polyimide
- semiconductor package
- lead frame
- layer
- lead
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
본 발명은 반도체 패키지의 리드프레임 제작방법 및 이를 이용한 반도체 패키지의 제조공정과 구조에 관한 것으로, 리드프레임의 재료인 구리(Cu)에 폴리이미드(Polyimide)를 코팅하여 폴리이미드(PI)층을 형성한 후, 스템핑(Stamping)에 의해 칩 탑재판과 리드 및 타이바 등을 형성하여 리드 프레임을 제작하는 것으로, 상기 폴리이미드(PI)에 의해 컴파운드와의 접착력을 향상시키고, 계면박리 및 크랙의 발생을 방지하여 패키지의 신뢰성을 향상시킬 수 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2도는 본 발명에 따른 반도체 패키지의 구조를 나타낸 단면도.
Claims (10)
- 리드프레임의 재료인 구리(Cu)에 폴리이미드(Polyimide)를 코팅하여 폴리이미드(PI)층을 형성한 후, 스템핑(Stamping)에 의해 칩 탑재판과 리드 및 타이바 등을 형성하여 반도체 패키지의 리드프레임 제작 방법.
- 제 1항에 있어서, 상기 폴리이미드(PI)층은 형성전에 은(Ag) 도금을 하는 것을 특징으로 하는 반도체 패키지의 리드프레임 제작방법.
- 제 1항에 있어서, 상기 폴리이미드(PI)층의 형성후에 은(Ag) 도금을 하는 것을 특징으로 하는 반도체 패키지의 리드프레임 제작방법.
- 제 2항 또는 제 3항에 있어서, 상기 은(Ag) 도금은 부분적으로 도금한 것을 특징으로 하는 반도체 패키지의 리드프레임 제작방법.
- 제 1항에 있어서, 상기 폴리이미드(PI)를 갖는 리드프레임에 블랙 산화(Black Oxide)층을 처리한 것을 특징으로 하는 반도체 패키지의 리드프레임 제작방법.
- 둘레에 다수의 리드가 배열되고, 상기 다수의 리드 중앙부에는 반도체 칩이 탑재되는 칩 탑재판이 구비되며, 상기 칩 탑재판은 다운셋을 가지면서 일체로 형성된 타이바에 연결 고정된 리드프레임에 있어서, 상기 리드프레임의 저면에 폴리이미드(Polyimide)층이 접착된 것을 특징으로 하는 반도체 패키지의 리드프레임 구조.
- 제 6항에 있어서, 상기 폴리이미드(PI)층을 갖는 리드프레임에 블랙 산화(Black Oxide)처리 된 것을 특징으로 하는 반도체 패키지의 리드프레임 제작방법.
- 다이본딩공정, 와이어본딩공정, 몰딩공정, 트림공정, 마킹공정, 포밍공정 등으로 이루어진 반도체 패키지 제조공정에 있어서, 상기 트림공정 후에 외부로 인출된 리드의 저면에 접착되어 있는 플로이미드(PI)층을 제거하는 폴리이미드 스트립핑(Polyimide Stripping)공정, 상기 공정을 거친 후 솔더 도금하는 솔더 플에이팅(Solder Plating)공정을 포함하는 것을 특징으로 하는 반도체 패키지의 제조공정.
- 제 8항에 있어서, 폴리이미드 스트립핑(Polyimide Stripping)공정은 강알칼리를 사용하여 폴리이미드(PI)를 제거하는 것을 특징으로 하는 반도체 패키지의 제조공정.
- 칩 탑재판의 상부에 에폭시에 의해 반도체 칩이 부착되고, 상기 반도체 칩 상의 칩패드와 리드는 와이어로 본딩되며, 그 외부는 산화 및 부식을 방지하기 위하여 컴파운드로 몰딩된 반도체 패키지 구조에 있어서, 상기 칩 탑재판과 리드의 저면에 폴리이미드(PI)가 접착된 것을 특징으로 하는 반도체 패키지 구조.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950041843A KR100198313B1 (ko) | 1995-11-17 | 1995-11-17 | 반도체패키지의 리드프레임 제조방법 및 이를 이용한 반도체패키지의 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950041843A KR100198313B1 (ko) | 1995-11-17 | 1995-11-17 | 반도체패키지의 리드프레임 제조방법 및 이를 이용한 반도체패키지의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970030743A true KR970030743A (ko) | 1997-06-26 |
KR100198313B1 KR100198313B1 (ko) | 1999-06-15 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019950041843A KR100198313B1 (ko) | 1995-11-17 | 1995-11-17 | 반도체패키지의 리드프레임 제조방법 및 이를 이용한 반도체패키지의 제조방법 |
Country Status (1)
Country | Link |
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KR (1) | KR100198313B1 (ko) |
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1995
- 1995-11-17 KR KR1019950041843A patent/KR100198313B1/ko not_active IP Right Cessation
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KR100198313B1 (ko) | 1999-06-15 |
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