KR970030341A - How to Form Contact Spacers - Google Patents

How to Form Contact Spacers Download PDF

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Publication number
KR970030341A
KR970030341A KR1019950039933A KR19950039933A KR970030341A KR 970030341 A KR970030341 A KR 970030341A KR 1019950039933 A KR1019950039933 A KR 1019950039933A KR 19950039933 A KR19950039933 A KR 19950039933A KR 970030341 A KR970030341 A KR 970030341A
Authority
KR
South Korea
Prior art keywords
contact
form contact
insulating layer
interlayer insulating
teos
Prior art date
Application number
KR1019950039933A
Other languages
Korean (ko)
Other versions
KR100365762B1 (en
Inventor
박인옥
정영석
김의식
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950039933A priority Critical patent/KR100365762B1/en
Publication of KR970030341A publication Critical patent/KR970030341A/en
Application granted granted Critical
Publication of KR100365762B1 publication Critical patent/KR100365762B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 반도체 소자 제조공정중 전도층 물질 간의 전기적 특성의 향상을 위하여 콘택 부위에 적용되는 콘택 스페이서의 물질을 증착하는 과정에서 저온에서 TEOS/SiH4/O2가스를 사용함으로써 양호한 층덮힘(STEP-COVERAGE) 특성을 유지하면서 콘택 홀 측벽의 BPSG막의 플로우 현상을 방지하는 방법이다.The present invention provides a good layer covering by using TEOS / SiH 4 / O 2 gas at low temperature in the process of depositing the material of the contact spacer applied to the contact portion to improve the electrical properties between the conductive layer materials during the semiconductor device manufacturing process. It is a method of preventing the flow phenomenon of the BPSG film on the sidewall of the contact hole while maintaining the -COVERAGE characteristic.

Description

콘택 스페이서 형성방법How to Form Contact Spacers

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따라 다이나믹 램의 비트라인 콘택 스페이서가 형성된 상태의 단면도이다.2 is a cross-sectional view of a bit line contact spacer of a dynamic RAM according to the present invention.

Claims (3)

반도체 소자의 콘택 스페이서 형성 방법에 있어서; 층간절연막을 식각하여 콘택 홀을 형성하는 단계; 상기 층간절연막이 플로우되지 않는 온도에서 TEOS/SiH4/O2가스를 사용하여 상기 콘택 홀 측벽에 스페이서를 형성하는 단계를 포함하는 것을 특징으로 하는 콘택 스페이서 형성 방법.A contact spacer forming method of a semiconductor device; Etching the interlayer insulating film to form contact holes; Forming a spacer on a sidewall of the contact hole using TEOS / SiH 4 / O 2 gas at a temperature at which the interlayer insulating film does not flow. 제1항에 있어서, 상기 층간절연막은 650℃ 이상에서 플로우가 발생하는 불순물이 도핑된 절연막을 포함하는 것을 특징으로 하는 콘택 스페이서 형성 방법.The method of claim 1, wherein the interlayer insulating layer comprises an insulating layer doped with impurities that generate a flow at 650 ° C. or higher. 제2항에 있어서; 상기 불순물이 도핑된 절연막은 BPSG 막인 것을 특징으로 하는 콘택 스페이서 형성 방법.The method of claim 2; And wherein the insulating layer doped with impurities is a BPSG film.
KR1019950039933A 1995-11-06 1995-11-06 A method for forming contact spacer of semiconductor device KR100365762B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950039933A KR100365762B1 (en) 1995-11-06 1995-11-06 A method for forming contact spacer of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950039933A KR100365762B1 (en) 1995-11-06 1995-11-06 A method for forming contact spacer of semiconductor device

Publications (2)

Publication Number Publication Date
KR970030341A true KR970030341A (en) 1997-06-26
KR100365762B1 KR100365762B1 (en) 2003-03-03

Family

ID=37491066

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950039933A KR100365762B1 (en) 1995-11-06 1995-11-06 A method for forming contact spacer of semiconductor device

Country Status (1)

Country Link
KR (1) KR100365762B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100790965B1 (en) * 2002-03-09 2008-01-02 삼성전자주식회사 Semiconductor device prevented ring defect and method for manufacturing the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06196433A (en) * 1992-12-24 1994-07-15 Sanyo Electric Co Ltd Method for formation of contact hole in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100790965B1 (en) * 2002-03-09 2008-01-02 삼성전자주식회사 Semiconductor device prevented ring defect and method for manufacturing the same

Also Published As

Publication number Publication date
KR100365762B1 (en) 2003-03-03

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