KR970029888A - Package Burn-in Test Circuit of Semiconductor Memory - Google Patents

Package Burn-in Test Circuit of Semiconductor Memory Download PDF

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Publication number
KR970029888A
KR970029888A KR1019950044852A KR19950044852A KR970029888A KR 970029888 A KR970029888 A KR 970029888A KR 1019950044852 A KR1019950044852 A KR 1019950044852A KR 19950044852 A KR19950044852 A KR 19950044852A KR 970029888 A KR970029888 A KR 970029888A
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South Korea
Prior art keywords
test
predetermined
circuit
response
semiconductor memory
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KR1019950044852A
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Korean (ko)
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KR100193448B1 (en
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강경우
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김광호
삼성전자 주식회사
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Priority to KR1019950044852A priority Critical patent/KR100193448B1/en
Publication of KR970029888A publication Critical patent/KR970029888A/en
Application granted granted Critical
Publication of KR100193448B1 publication Critical patent/KR100193448B1/en

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  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

1. 청구범위에 기재된 발명이 속하는 기술 분야;1. the technical field to which the invention described in the claims belongs;

본 발명은 반도체 메모리의 테스트회로에 관한 것으로, 특히 모든 워드라인을 동시에 인에이블시켜 테스트하므로써 테스트시간을 줄인 반도체 메모리의 패키지 번인 테스트회로에 관한 것이다.The present invention relates to a test circuit of a semiconductor memory, and more particularly, to a package burn-in test circuit of a semiconductor memory which reduces test time by enabling all word lines to be tested at the same time.

2. 발명이 해결하려고 하는 기술적 과제;2. The technical problem to be solved by the invention;

패키지 테스트과정에서 발생되는 시간지연을 해결하고자 한다.We want to solve the time delay that occurs during package testing.

3. 발명의 해결방법의 요지;3. Summary of the Solution of the Invention;

소정의 스트레스전압이 인가되는 소정의 핀과, 상기 핀에 유입되는 스트레스전압에 응답하여 소정의 모드에서 인에이블되는 인에이블신호 발생회로와, 상기 인에이블신호 발생회로의 출력에 응답하여 소정의 제어신호를 출력하는 제어신호 발생회로와, 상기 제어신호 발생회로의 출력에 응답하여 소정의 테스트전압을 출력하는 차아지공급수단을 구비하고, 상기 제어신호 발생회로의 출력에 응답하여 다수의 워드라인에 테스트전압을 공급함을 특징으로 하는 반도체 메모리 장치의 패키지 번인 테스트회로를 구현하므로써 패키지상태에서 고속의 테스트를 실행할 수 있게 된다.A predetermined pin to which a predetermined stress voltage is applied, an enable signal generating circuit enabled in a predetermined mode in response to the stress voltage flowing into the pin, and a predetermined control in response to an output of the enable signal generating circuit A control signal generation circuit for outputting a signal, and charge supply means for outputting a predetermined test voltage in response to the output of the control signal generation circuit, and in response to the output of the control signal generation circuit; By implementing the package burn-in test circuit of the semiconductor memory device characterized by supplying a test voltage, it is possible to execute a high-speed test in the package state.

4. 발명의 중요한 용도;4. Significant use of the invention;

패키지상태에서 고속으로 테스트동작을 실행하는 반도체 메모리장치.A semiconductor memory device which performs a test operation at a high speed in a packaged state.

Description

반도체 메모리의 패키지 번인 테스트회로Package Burn-in Test Circuit of Semiconductor Memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 실시예에 따른 테스트과정을 보여주는 도면.1 is a view showing a test process according to an embodiment of the present invention.

Claims (5)

반도체 메모리 장치의 패키지 번인 테스트회로에 있어서, 소정의 스트레스전압이 인가되는 소정의 핀과, 상기 핀에 유입되는 스트레스전압에 응답하여 소정의 모드에서 인에이블되는 인에이블신호 발생회로와, 상기 인인에이블신호 발생회로의 출력에 응답하여 소정의 제어신호를 출력하는 제어신호 발생회로와, 상기 제어신호 발생회로의 출력에 응답하여 소정의 테스트전압을 출력하는 차아지공급수단을 구비하고, 상기 제어신호 발생회로의 출력에 응답하여 다수의 워드라인에 테스트전압을 공급함을 특징으로 하는 반도체 메모리 장치의 패키지 번인 테스트회로.A package burn-in test circuit of a semiconductor memory device, comprising: a predetermined pin to which a predetermined stress voltage is applied; an enable signal generating circuit that is enabled in a predetermined mode in response to the stress voltage flowing into the pin; A control signal generation circuit for outputting a predetermined control signal in response to the output of the signal generation circuit, and charge supply means for outputting a predetermined test voltage in response to the output of the control signal generation circuit; A package burn-in test circuit for supplying a test voltage to a plurality of word lines in response to an output of the circuit. 제1항에 있어서, 상기 소정의 핀이 어드레스핀 또는 아웃풋 인에이블핀임을 특징으로 하는 반도체 메모리 장치의 패키지 번인 테스트회로.The package burn-in test circuit of claim 1, wherein the predetermined pin is an address pin or an output enable pin. 제1항에 있어서, 상기 소정의 모드가 멀티비트를 테스트하는 WCBR모드임을 특징으로 하는 반도체 메모리 장치의 패키지 번인 테스트회로.The package burn-in test circuit of claim 1, wherein the predetermined mode is a WCBR mode for testing multi-bits. 제1항에 있어서, 상기 다수의 워드라인이 모드 워드라인 또는 반의 워드라인임을 특징으로 하는 반도체 메모리 장치의 패키지 번인 테스트회로.The package burn-in test circuit of claim 1, wherein the plurality of word lines are a mode word line or a half word line. 제1항에 있어서, 상기 테스트동작이 타이밍이 전환되어도 해당 컨디션이 내부적으로 유지되며 다른 모드 동작을 실행하는 사이클로 전환될 때 종료됨을 특징으로 하는 반도체 메모리 장치의 패키지 번인 테스트회로.2. The package burn-in test circuit of claim 1, wherein the test operation is terminated when the test operation is switched internally even when timing is changed and is switched to a cycle for executing another mode operation.
KR1019950044852A 1995-11-29 1995-11-29 Package Burn-in Test Circuit of Semiconductor Memory KR100193448B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950044852A KR100193448B1 (en) 1995-11-29 1995-11-29 Package Burn-in Test Circuit of Semiconductor Memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950044852A KR100193448B1 (en) 1995-11-29 1995-11-29 Package Burn-in Test Circuit of Semiconductor Memory

Publications (2)

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KR970029888A true KR970029888A (en) 1997-06-26
KR100193448B1 KR100193448B1 (en) 1999-06-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498413B1 (en) * 1997-12-08 2005-09-08 삼성전자주식회사 Wordline control circuit for semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498413B1 (en) * 1997-12-08 2005-09-08 삼성전자주식회사 Wordline control circuit for semiconductor memory device

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KR100193448B1 (en) 1999-06-15

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